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| 1 2 3 4 6 7 5 11 8 9 10 dsp56309 overview signal/connection descriptions memory configuration core configuration general purpose i/o host interface (hi08) enhanced synchronous serial interface serial communication interface (sci) timer module on-chip emulation module jtag port c bsdl listing i index d programming reference a bootstrap program b equates f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1 2 3 4 6 7 5 11 8 9 10 dsp56309 overview signal/connection descriptions memory configuration core configuration general purpose i/o host interface (hi08) enhanced synchronous serial interface serial communication interface (sci) timer module on-chip emulation module jtag port c bsdl listing i index d programming reference a bootstrap program b equates f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 24-bit digital signal processor user?s manual motorola, incorporated semiconductor products sector dsp division 6501 william cannon drive west austin, tx 78735-8598 rev. 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . this document (and other documents) can be viewed on the world wide web at http://www.mot.com/sps/dsp/documentation/ this manual is one of a set of three documents. you need the following manuals to have complete product information: family manual, user?s manual, and technical data. once ? is a trademark of motorola, inc. intel is a registered trademark of the intel corporation. all other trademarks are those of their respective owners. ? motorola inc., 1998 reg. u.s. pat. & tm. off. order this document by dsp56309um/d motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. buyer agrees to notify motorola of any such intended end use whereupon motorola shall determine availability and suitability of its product or products for the use intended. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal employment opportunity /affirmative action employer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d iii table of contents section 1 dsp56309 overview . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 manual organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4 dsp56309 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 dsp56309 core description . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.1 general features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.2 hardware debugging support . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.3 reduced power dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.6 dsp56300 core functional blocks . . . . . . . . . . . . . . 1-8 1.6.1 data alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.6.1.1 data alu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.6.1.2 multiplier-accumulator (mac) . . . . . . . . . . . . . . . . . . . . 1-9 1.6.2 address generation unit (agu) . . . . . . . . . . . . . . . . . . . . 1-9 1.6.3 program control unit (pcu) . . . . . . . . . . . . . . . . . . . . . . 1-10 1.6.4 pll and clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.6.5 jtag tap and once module . . . . . . . . . . . . . . . . . . . . . 1-11 1.6.6 on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.6.7 off-chip memory expansion . . . . . . . . . . . . . . . . . . . . . . 1-12 1.7 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.8 dsp56309 block diagram . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . 1-15 1.10 dsp56309 architecture overview . . . . . . . . . . . . . 1-15 1.10.1 gpio functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.10.2 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.10.3 enhanced synchronous serial interface (essi) . . . . . . . 1-16 1.10.4 serial communications interface (sci) . . . . . . . . . . . . . . 1-16 1.10.5 timer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 section 2 signal/connection descriptions. . . . . . . . 2-1 2.1 signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . iv dsp56309um/d motorola 2.3 ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.4 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 phase-locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.6 external memory expansion port (port a). . . . . 2-9 2.6.1 external address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.6.2 external data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.6.3 external bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.7 interrupt and mode control . . . . . . . . . . . . . . . . . 2-14 2.8 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.8.1 host port usage considerations. . . . . . . . . . . . . . . . . . . 2-16 2.8.2 host port configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.9 enhanced synchronous serial interface . . . . 2-24 2.9.1 essi0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.9.2 essi1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.10 serial communication interface (sci) . . . . . . . . . 2-32 2.11 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.12 once/jtag interface. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 section 3 memory configuration . . . . . . . . . . . . . . . . . 3-1 3.1 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.1 program memory space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2 data memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2.1 x data memory space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.2.2 y data memory space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.3 memory space configuration . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2 ram configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 on-chip program memory (program ram) . . . . . . . . . . . 3-6 3.2.2 on-chip x data memory (x data ram) . . . . . . . . . . . . . . 3-6 3.2.3 on-chip y data memory (y data ram) . . . . . . . . . . . . . . 3-7 3.2.4 bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 memory configurations . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.1 memory space configurations . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.2 ram configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . 3-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d v section 4 core configuration . . . . . . . . . . . . . . . . . . . . 4-1 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 bootstrap program. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 mode 0: expanded mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.2 modes 1 to 7: reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.3 mode 8: expanded mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.4 mode 9: boot from byte-wide external memory . . . . . . . . 4-7 4.3.5 mode a: boot from sci . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.6 mode b: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.7 modes c, d, e, f: boot from hi08 . . . . . . . . . . . . . . . . . . . 4-8 4.3.7.1 mode c: in isa/dsp5630x mode (8-bit bus) . . . . . . . 4-8 4.3.7.2 mode d: in hc11 non-multiplexed mode . . . . . . . . . . 4-8 4.3.7.3 mode e: in 8051 multiplexed bus mode . . . . . . . . . . . 4-9 4.3.7.4 mode f: in 68302/68360 bus mode . . . . . . . . . . . . . . . 4-9 4.4 interrupt sources and priorities . . . . . . . . . . . . . 4-9 4.4.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.2 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3 interrupt source priorities within an ipl . . . . . . . . . . . . . 4-14 4.5 dma request sources . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.6 operating mode register (omr) . . . . . . . . . . . . . . . 4-17 4.7 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.7.1 pctl pll multiplication factor bits 0e11 . . . . . . . . . . . . 4-18 4.7.2 pctl xtal disable bit (xtld) bit 16. . . . . . . . . . . . . . . 4-18 4.7.3 pctl predivider factor bits (pd0epd3) bits 20e23 . . . . 4-18 4.8 device identification register (idr) . . . . . . . . . . . 4-18 4.9 aa control registers (aar0eaar3) . . . . . . . . . . . . 4-19 4.10 jtag boundary scan register (bsr) . . . . . . . . . . . 4-20 section 5 general-purpose i/o . . . . . . . . . . . . . . . . . . . . 5-1 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.1 port b signals and registers. . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 port c signals and registers. . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.3 port d signals and registers. . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.4 port e signals and registers. . . . . . . . . . . . . . . . . . . . . . . 5-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . vi dsp56309um/d motorola 5.2.5 triple timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 section 6 host interface (hi08) . . . . . . . . . . . . . . . . . . . 6-1 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 hi08 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 host to dsp core interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.2 hi08-to-host processor interface . . . . . . . . . . . . . . . . . . . 6-4 6.3 hi08 host port signals. . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 hi08 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5 hi08 dsp side programmer?s model. . . . . . . . . . . . . 6-8 6.5.1 host receive data register (hrx). . . . . . . . . . . . . . . . . . 6-8 6.5.2 host transmit data register (htx) . . . . . . . . . . . . . . . . . 6-9 6.5.3 host control register (hcr). . . . . . . . . . . . . . . . . . . . . . . 6-9 6.5.3.1 hcr host receive interrupt enable (hrie) bit 0 . . . 6-10 6.5.3.2 hcr host transmit interrupt enable (htie) bit 1 . . . 6-10 6.5.3.3 hcr host command interrupt enable (hcie) bit 2 . . 6-10 6.5.3.4 hcr host flags 2,3 (hf[3:2]) bits 3, 4 . . . . . . . . . . . 6-10 6.5.3.5 hcr reserved bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.4 host status register (hsr) . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.4.1 hsr host receive data full (hrdf) bit 0 . . . . . . . . 6-11 6.5.4.2 hsr host transmit data empty (htde) bit 1 . . . . . . 6-11 6.5.4.3 hsr host command pending (hcp) bit 2 . . . . . . . . 6-11 6.5.4.4 hsr host flags 0, 1 (hf[1:0]) bits 3, 4 . . . . . . . . . . . 6-11 6.5.4.5 hsr reserved bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.5 host base address register (hbar) . . . . . . . . . . . . . . . 6-12 6.5.5.1 hbar base address (ba[10:3]) bits 0-7 . . . . . . . . . . 6-12 6.5.5.2 hbar reserved bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.6 host port control register (hpcr). . . . . . . . . . . . . . . . . 6-12 6.5.6.1 hpcr host gpio port enable (hgen) bit 0 . . . . . . . 6-13 6.5.6.2 hpcr host address line 8 enable (ha8en) bit 1 . . 6-13 6.5.6.3 hpcr host address line 9 enable (ha9en) bit 2 . . 6-13 6.5.6.4 hpcr host chip select enable (hcsen) bit 3 . . . . . 6-13 6.5.6.5 hpcr host request enable (hren) bit 4 . . . . . . . . 6-14 6.5.6.6 hpcr host acknowledge enable (haen) bit 5. . . . . 6-14 6.5.6.7 hpcr host enable (hen) bit 6 . . . . . . . . . . . . . . . . . 6-14 6.5.6.8 hpcr reserved bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d vii 6.5.6.9 hpcr host request open drain (hrod) bit 8 . . . . . 6-14 6.5.6.10 hpcr host data strobe polarity (hdsp) bit 9. . . . . . 6-14 6.5.6.11 hpcr host address strobe polarity (hasp) bit 10 . . 6-15 6.5.6.12 hpcr host multiplexed bus (hmux) bit 11 . . . . . . . . 6-15 6.5.6.13 hpcr host dual data strobe (hdds) bit 12 . . . . . . . 6-15 6.5.6.14 hpcr host chip select polarity (hcsp) bit 13 . . . . . 6-16 6.5.6.15 hpcr host request polarity (hrp) bit 14 . . . . . . . . . 6-16 6.5.6.16 hpcr host acknowledge polarity (hap) bit 15 . . . . . 6-16 6.5.7 host data direction register (hddr) . . . . . . . . . . . . . . . 6-17 6.5.8 host data register (hdr) . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.5.9 dsp side registers after reset . . . . . . . . . . . . . . . . . . . 6-18 6.5.10 host interface dsp core interrupts . . . . . . . . . . . . . . . . . 6-19 6.6 hi08-external host programmer?s model . . . . . 6-20 6.6.1 interface control register (icr) . . . . . . . . . . . . . . . . . . . 6-22 6.6.1.1 icr receive request enable (rreq) bit 0 . . . . . . . . 6-23 6.6.1.2 icr transmit request enable (treq) bit 1. . . . . . . . 6-23 6.6.1.3 icr double host request (hdrq) bit 2. . . . . . . . . . . 6-23 6.6.1.4 icr host flag 0 (hf0) bit 3 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.5 icr host flag 1 (hf1) bit 4 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.6 icr host little endian (hlend) bit 5 . . . . . . . . . . . . . 6-24 6.6.1.7 icr reserved bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.6.1.8 icr initialize bit (init) bit 7 . . . . . . . . . . . . . . . . . . . . 6-24 6.6.2 command vector register (cvr) . . . . . . . . . . . . . . . . . . 6-25 6.6.2.1 cvr host vector (hv[6:0]) bits 0e6 . . . . . . . . . . . . . . 6-25 6.6.2.2 cvr host command bit (hc) bit 7. . . . . . . . . . . . . . . 6-26 6.6.3 interface status register (isr) . . . . . . . . . . . . . . . . . . . . 6-26 6.6.3.1 isr receive data register full (rxdf) bit 0 . . . . . . . 6-26 6.6.3.2 isr transmit data register empty (txde) bit 1 . . . . 6-27 6.6.3.3 isr transmitter ready (trdy) bit 2 . . . . . . . . . . . . . 6-27 6.6.3.4 isr host flag 2 (hf2) bit 3 . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.5 isr host flag 3 (hf3) bit 4 . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.6 isr reserved bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.6.3.7 isr host request (hreq) bit 7 . . . . . . . . . . . . . . . . . 6-27 6.6.4 interrupt vector register (ivr) . . . . . . . . . . . . . . . . . . . . 6-28 6.6.5 receive byte registers (rxh: rxm: rxl) . . . . . . . . . . . 6-28 6.6.6 transmit byte registers (txh:txm:txl) . . . . . . . . . . . . 6-29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . viii dsp56309um/d motorola 6.6.7 host side registers after reset . . . . . . . . . . . . . . . . . . . 6-30 6.6.8 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6.7 servicing the host interface . . . . . . . . . . . . . . . . 6-31 6.7.1 hi08 host processor data transfer . . . . . . . . . . . . . . . . 6-31 6.7.2 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.7.3 servicing interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.8 hi08 programming model quick reference. . . . 6-34 section 7 enhanced synchronous serial interface (essi) 7-1 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 enhancements to the essi . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 essi data and control signals . . . . . . . . . . . . . . . . 7-4 7.3.1 serial transmit data (std) signal . . . . . . . . . . . . . . . . . . 7-4 7.3.2 serial receive data signal (srd) . . . . . . . . . . . . . . . . . . 7-4 7.3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.4 serial control signal (sc0) . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.5 serial control signal (sc1) . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.6 serial control signal (sc2) . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4 essi programming model . . . . . . . . . . . . . . . . . . . . . . 7-8 7.4.1 essi control register a (cra). . . . . . . . . . . . . . . . . . . . 7-11 7.4.1.1 cra prescale modulus select pm[7:0] bits 7e0 . . . . 7-11 7.4.1.2 cra reserved bits 8e10 . . . . . . . . . . . . . . . . . . . . . . 7-11 7.4.1.3 cra prescaler range (psr) bit 11 . . . . . . . . . . . . . . 7-11 7.4.1.4 cra frame rate divider control dc[4:0] bits 16e12 7-12 7.4.1.5 cra reserved bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.1.6 cra alignment control (alc) bit 18 . . . . . . . . . . . . . 7-13 7.4.1.7 cra word-length control (wl[2:0]) bits 21e19 . . . . . 7-14 7.4.1.8 cra select sc1 (ssc1) bit 22 . . . . . . . . . . . . . . . . . 7-14 7.4.1.9 cra reserved bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.4.2 essi control register b (crb). . . . . . . . . . . . . . . . . . . . 7-15 7.4.2.1 crb serial output flags (of0, of1) bits 0, 1. . . . . . 7-15 7.4.2.1.1 crb serial output flag 0 (of0) bit 0 . . . . . . . . . . 7-15 7.4.2.1.2 crb serial output flag 1 (of1) bit 1 . . . . . . . . . . 7-16 7.4.2.2 crb serial control direction 0 (scd0) bit 2 . . . . . . . 7-16 7.4.2.3 crb serial control direction 1 (scd1) bit 3 . . . . . . . 7-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d ix 7.4.2.4 crb serial control direction 2 (scd2) bit 4 . . . . . . . 7-16 7.4.2.5 crb clock source direction (sckd) bit 5 . . . . . . . . . 7-16 7.4.2.6 crb shift direction (shfd) bit 6 . . . . . . . . . . . . . . . . 7-17 7.4.2.7 crb frame sync length fsl[1:0] bits 7 and 8 . . . . . 7-17 7.4.2.8 crb frame sync relative timing (fsr) bit 9 . . . . . . 7-17 7.4.2.9 crb frame sync polarity (fsp) bit 10. . . . . . . . . . . . 7-17 7.4.2.10 crb clock polarity (ckp) bit 11. . . . . . . . . . . . . . . . . 7-18 7.4.2.11 crb synchronous /asynchronous (syn) bit 12. . . . . 7-18 7.4.2.12 crb essi mode select (mod) bit 13 . . . . . . . . . . . . 7-20 7.4.2.13 enabling, disabling essi data transmission . . . . . . . 7-22 7.4.2.14 crb essi transmit 2 enable (te2) bit 14 . . . . . . . . . 7-22 7.4.2.15 crb essi transmit 1 enable (te1) bit 15 . . . . . . . . . 7-23 7.4.2.16 crb essi transmit 0 enable (te0) bit 16 . . . . . . . . . 7-24 7.4.2.17 crb essi receive enable (re) bit 17. . . . . . . . . . . . 7-26 7.4.2.18 crb essi transmit interrupt enable (tie) bit 18. . . . 7-26 7.4.2.19 crb essi receive interrupt enable (rie) bit 19 . . . . 7-26 7.4.2.20 transmit last slot interrupt enable (tlie) bit 20 . . . . 7-26 7.4.2.21 receive last slot interrupt enable (rlie) bit 21 . . . . 7-27 7.4.2.22 transmit exception interrupt enable (teie) bit 22 . . . 7-27 7.4.2.23 receive exception interrupt enable (reie) bit 23 . . . 7-27 7.4.3 essi status register (ssisr). . . . . . . . . . . . . . . . . . . . . 7-27 7.4.3.1 ssisr serial input flag 0 (if0) bit 0 . . . . . . . . . . . . . 7-28 7.4.3.2 ssisr serial input flag 1 (if1) bit 1 . . . . . . . . . . . . . 7-28 7.4.3.3 ssisr transmit frame sync flag (tfs) bit 2 . . . . . . 7-28 7.4.3.4 ssisr receive frame sync flag (rfs) bit 3 . . . . . . 7-28 7.4.3.5 ssisr transmitter underrun error flag (tue) bit 4 . 7-29 7.4.3.6 ssisr receiver overrun error flag (roe) bit 5 . . . . 7-29 7.4.3.7 essi transmit data register empty (tde) bit 6 . . . . 7-29 7.4.3.8 essi receive data register full (rdf) bit 7 . . . . . . . 7-30 7.4.4 essi receive shift register . . . . . . . . . . . . . . . . . . . . . . 7-33 7.4.5 essi receive data register (rx) . . . . . . . . . . . . . . . . . . 7-33 7.4.6 essi transmit shift registers . . . . . . . . . . . . . . . . . . . . . 7-33 7.4.7 essi transmit data registers (tx0-2) . . . . . . . . . . . . . . 7-34 7.4.8 essi time slot register (tsr) . . . . . . . . . . . . . . . . . . . . 7-34 7.4.9 transmit slot mask registers (tsma, tsmb) . . . . . . . . 7-34 7.4.10 receive slot mask registers (rsma, rsmb). . . . . . . . . 7-35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x dsp56309um/d motorola 7.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7.5.1 essi after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7.5.2 essi initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7.5.3 essi exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 7.5.4 operating modes: normal, network, and on-demand . . 7-40 7.5.4.1 normal/network/on-demand mode selection . . . . . . 7-40 7.5.4.2 synchronous/asynchronous operating modes . . . . . 7-40 7.5.4.3 frame sync selection . . . . . . . . . . . . . . . . . . . . . . . . 7-41 7.5.4.3.1 frame sync signal format . . . . . . . . . . . . . . . . . . 7-41 7.5.4.3.2 frame sync length for multiple devices . . . . . . . . 7-41 7.5.4.3.3 word-length frame sync and data-word timing 7-41 7.5.4.3.4 frame sync polarity . . . . . . . . . . . . . . . . . . . . . . . 7-42 7.5.4.4 byte format (lsb/msb) for the transmitter . . . . . . . 7-42 7.5.5 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 7.6 gpio signals and registers. . . . . . . . . . . . . . . . . . . 7-43 7.6.1 port control register (pcr) . . . . . . . . . . . . . . . . . . . . . . 7-43 7.6.2 port direction register (prr) . . . . . . . . . . . . . . . . . . . . . 7-44 7.6.3 port data register (pdr) . . . . . . . . . . . . . . . . . . . . . . . . 7-45 section 8 serial communication interface (sci) . . 8-1 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 sci i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 receive data (rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.2 transmit data (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.3 sci serial clock (sclk) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3 sci programming model . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.1 sci control register (scr) . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3.1.1 scr word select (wds[0:2]) bits 0e2 . . . . . . . . . . . . 8-8 8.3.1.2 scr sci shift direction (ssftd) bit 3 . . . . . . . . . . . . 8-9 8.3.1.3 scr send break (sbk) bit 4 . . . . . . . . . . . . . . . . . . . . 8-9 8.3.1.4 scr wakeup mode select (wake) bit 5 . . . . . . . . . . 8-9 8.3.1.5 scr receiver wakeup enable (rwu) bit 6 . . . . . . . . 8-9 8.3.1.6 scr wired-or mode select (woms) bit 7. . . . . . . . 8-10 8.3.1.7 scr receiver enable (re) bit 8 . . . . . . . . . . . . . . . . 8-10 8.3.1.8 scr transmitter enable (te) bit 9 . . . . . . . . . . . . . . 8-10 8.3.1.9 scr idle line interrupt enable (ilie) bit 10. . . . . . . . 8-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xi 8.3.1.10 scr sci receive interrupt enable (rie) bit 11 . . . . . 8-11 8.3.1.11 scr sci transmit interrupt enable (tie) bit 12. . . . . 8-12 8.3.1.12 scr timer interrupt enable (tmie) bit 13 . . . . . . . . . 8-12 8.3.1.13 scr timer interrupt rate (stir) bit 14 . . . . . . . . . . . 8-12 8.3.1.14 scr sci clock polarity (sckp) bit 15 . . . . . . . . . . . . 8-12 8.3.1.15 receive with exception interrupt enable (reie) bit 168-13 8.3.2 sci status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.3.2.1 ssr transmitter empty (trne) bit 0 . . . . . . . . . . . . . 8-13 8.3.2.2 ssr transmit data register empty (tdre) bit 1 . . . 8-13 8.3.2.3 ssr receive data register full (rdrf) bit 2 . . . . . . 8-14 8.3.2.4 ssr idle line flag (idle) bit 3. . . . . . . . . . . . . . . . . . 8-14 8.3.2.5 ssr overrun error flag (or) bit 4. . . . . . . . . . . . . . . 8-14 8.3.2.6 ssr parity error (pe) bit 5 . . . . . . . . . . . . . . . . . . . . . 8-14 8.3.2.7 ssr framing error flag (fe) bit 6 . . . . . . . . . . . . . . . 8-15 8.3.2.8 ssr received bit 8 (r8) address bit 7 . . . . . . . . . . . 8-15 8.3.3 sci clock control register (sccr) . . . . . . . . . . . . . . . . 8-15 8.3.3.1 sccr clock divider (cd[11:0]) bits 11e0 . . . . . . . . . 8-16 8.3.3.2 sccr clock out divider (cod) bit 12 . . . . . . . . . . . . 8-16 8.3.3.3 sccr sci clock prescaler (scp) bit 13 . . . . . . . . . . 8-17 8.3.3.4 sccr receive clock mode source (rcm) bit 14 . . . 8-17 8.3.3.5 sccr transmit clock source bit (tcm) bit 15 . . . . . 8-18 8.3.4 sci data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.3.4.1 sci receive registers (srx) . . . . . . . . . . . . . . . . . . . 8-19 8.3.4.2 sci transmit registers . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.4.1 sci after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.4.2 sci initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.4.3 sci initialization example . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.4.4 preamble, break, and data transmission priority . . . . . . 8-26 8.4.5 sci exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.5 gpio signals and registers . . . . . . . . . . . . . . . . . . . 8-27 8.5.1 port e control register (pcre) . . . . . . . . . . . . . . . . . . . 8-27 8.5.2 port e direction register (prre) . . . . . . . . . . . . . . . . . . 8-27 8.5.3 port e data register (pdre) . . . . . . . . . . . . . . . . . . . . . 8-28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xii dsp56309um/d motorola section 9 triple timer module . . . . . . . . . . . . . . . . . . . . 9-1 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 triple timer module architecture . . . . . . . . . . . . 9-3 9.2.1 triple timer module block diagram . . . . . . . . . . . . . . . . . 9-3 9.2.2 timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3 triple timer module programming model. . . . . . 9-5 9.3.1 prescaler counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3.2 timer prescaler load register (tplr). . . . . . . . . . . . . . . 9-7 9.3.2.1 tplr prescaler preload value (pl[20:0]) bits 20-0 . . 9-7 9.3.2.2 tplr prescaler source (ps[1:0]) bits 22-21 . . . . . . . . 9-7 9.3.2.3 tplr reserved bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3 timer prescaler count register (tpcr). . . . . . . . . . . . . . 9-8 9.3.3.1 tpcr prescaler counter value (pc[20:0]) bits 20-0 . . 9-9 9.3.3.2 tpcr reserved bits 23-21 . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.4 timer control/status register (tcsr) . . . . . . . . . . . . . . . 9-9 9.3.4.1 timer enable (te) bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.4.2 timer overflow interrupt enable (toie) bit 1 . . . . . . . 9-9 9.3.4.3 timer compare interrupt enable (tcie) bit 2 . . . . . . 9-10 9.3.4.4 timer control (tc[3:0]) bits 4-7 . . . . . . . . . . . . . . . . . 9-10 9.3.4.5 inverter (inv) bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.4.6 timer reload mode (trm) bit 9 . . . . . . . . . . . . . . . . 9-13 9.3.4.7 direction (dir) bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.8 data input (di) bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.9 data output (do) bit 13 . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.3.4.10 prescaler clock enable (pce) bit 15 . . . . . . . . . . . . . 9-14 9.3.4.11 timer overflow flag (tof) bit 20 . . . . . . . . . . . . . . . 9-14 9.3.4.12 timer compare flag (tcf) bit 21 . . . . . . . . . . . . . . . 9-15 9.3.4.13 tcsr reserved bits 3, 10, 14, 16-19, 22, 23 . . . . . . 9-15 9.3.5 timer load register (tlr) . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.3.6 timer compare register (tcpr) . . . . . . . . . . . . . . . . . . 9-16 9.3.7 timer count register (tcr) . . . . . . . . . . . . . . . . . . . . . . 9-16 9.4 timer operational modes. . . . . . . . . . . . . . . . . . . . . 9-16 9.4.1 timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.1.1 timer gpio (mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.1.2 timer pulse (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.1.3 timer toggle (mode 2) . . . . . . . . . . . . . . . . . . . . . . . . 9-19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xiii 9.4.1.4 timer event counter (mode 3) . . . . . . . . . . . . . . . . . . 9-20 9.4.2 signal measurement modes . . . . . . . . . . . . . . . . . . . . . . 9-20 9.4.2.1 measurement accuracy . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.4.2.2 measurement input width (mode 4) . . . . . . . . . . . . . . 9-21 9.4.2.3 measurement input period (mode 5) . . . . . . . . . . . . . 9-22 9.4.2.4 measurement capture (mode 6) . . . . . . . . . . . . . . . . . 9-23 9.4.3 pulse width modulation (pwm, mode 7) . . . . . . . . . . . . . 9-24 9.4.4 watchdog modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 9.4.4.1 watchdog pulse (mode 9). . . . . . . . . . . . . . . . . . . . . . 9-25 9.4.4.2 watchdog toggle (mode 10). . . . . . . . . . . . . . . . . . . . 9-26 9.4.5 reserved modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.4.6 special cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.4.6.1 timer behavior during wait. . . . . . . . . . . . . . . . . . . . . 9-27 9.4.6.2 timer behavior during stop . . . . . . . . . . . . . . . . . . . . 9-27 9.4.7 dma trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 section 10 on-chip emulation module . . . . . . . . . . . . . 10-1 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 once module signals . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 debug event (de) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4 once controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4.1 once command register (ocr) . . . . . . . . . . . . . . . . . . 10-5 10.4.1.1 register select (rs4ers0) bits 0e4 . . . . . . . . . . . . . 10-5 10.4.1.2 exit command (ex) bit 5 . . . . . . . . . . . . . . . . . . . . . . 10-5 10.4.1.3 go command (go) bit 6 . . . . . . . . . . . . . . . . . . . . . . 10-6 10.4.1.4 read/write command (r/w ) bit 7 . . . . . . . . . . . . . . . 10-6 10.4.2 once decoder (odec). . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.4.3 once status and control register (oscr) . . . . . . . . . . 10-8 10.4.3.1 trace mode enable (tme) bit 0 . . . . . . . . . . . . . . . . . 10-8 10.4.3.2 interrupt mode enable (ime) bit 1. . . . . . . . . . . . . . . . 10-8 10.4.3.3 software debug occurrence (swo) bit 2. . . . . . . . . . 10-8 10.4.3.4 memory breakpoint occurrence (mbo) bit 3 . . . . . . . 10-8 10.4.3.5 trace occurrence (to) bit 4. . . . . . . . . . . . . . . . . . . . 10-9 10.4.3.6 reserved ocsr bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.4.3.7 core status (os0, os1) bits 6-7 . . . . . . . . . . . . . . . . 10-9 10.4.3.8 reserved bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xiv dsp56309um/d motorola 10.5 once memory breakpoint logic. . . . . . . . . . . . . . . 10-9 10.5.1 once memory address latch (omal). . . . . . . . . . . . . 10-11 10.5.2 once memory limit register 0 (omlr0). . . . . . . . . . . 10-11 10.5.3 once memory address comparator 0 (omac0) . . . . . 10-11 10.5.4 once memory limit register 1 (omlr1). . . . . . . . . . . 10-11 10.5.5 once memory address comparator 1 (omac1) . . . . . 10-11 10.5.6 once breakpoint control register (obcr) . . . . . . . . . 10-12 10.5.6.1 memory breakpoint select (mbs0embs1) . . . . . . . 10-12 10.5.6.2 breakpoint 0 read/write select (rw00erw01) . . . 10-12 10.5.6.3 breakpoint 0 condition code select (cc00ecc01). 10-13 10.5.6.4 breakpoint 1 read/write select (rw10erw11) . . . 10-13 10.5.6.5 breakpoint 1 condition code select (cc10ecc11). 10-14 10.5.6.6 breakpoint 0 and 1 event select (bt0ebt1) . . . . . . 10-14 10.5.6.7 once memory breakpoint counter (ombc) . . . . . . 10-14 10.5.6.8 reserved bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.6 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.7 methods of entering debug mode . . . . . . . . . . . 10-16 10.7.1 external debug request during reset assertion . . . 10-16 10.7.2 external debug request during normal activity . . . . . 10-16 10.7.3 executing the jtag debug_request instruction . . 10-17 10.7.4 external debug request during stop . . . . . . . . . . . . . . 10-17 10.7.5 external debug request during wait . . . . . . . . . . . . . . 10-17 10.7.6 software request during normal activity . . . . . . . . . . . 10-18 10.7.7 enabling trace mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.7.8 enabling memory breakpoints . . . . . . . . . . . . . . . . . . . 10-18 10.8 pipeline information and ogdb register. . . . . 10-18 10.8.1 once pdb register (opdbr) . . . . . . . . . . . . . . . . . . . 10-19 10.8.2 once pil register (opilr) . . . . . . . . . . . . . . . . . . . . . 10-19 10.8.3 once gdb register (ogdbr). . . . . . . . . . . . . . . . . . . 10-20 10.9 debugging resources . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.9.1 once pab register for fetch (opabfr) . . . . . . . . . . 10-20 10.9.2 pab register for decode (opabdr) . . . . . . . . . . . . . . 10-20 10.9.3 once pab register for execute (opabex) . . . . . . . . 10-20 10.9.4 trace buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.10 serial protocol description . . . . . . . . . . . . . . . . 10-22 10.11 target site debug system requirements . . . . 10-23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xv 10.12 once module examples . . . . . . . . . . . . . . . . . . . . . . 10-23 10.12.1 checking whether the chip has entered debug mode 10-24 10.12.2 polling the jtag instruction shift register . . . . . . . . . . 10-24 10.12.3 saving pipeline information . . . . . . . . . . . . . . . . . . . . . . 10-25 10.12.4 reading the trace buffer. . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.12.5 displaying a specified register . . . . . . . . . . . . . . . . . . . 10-26 10.12.6 displaying x memory area starting at address $xxxx . 10-26 10.12.7 returning from debug to normal mode (same program)10-28 10.12.8 returning from debug to normal mode (new program) 10-28 10.13 jtag port/once module interaction . . . . . . . . . 10-29 section 11 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2 jtag signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.1 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.3 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.4 test data output (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.5 test reset (trst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 boundary scan register (bsr) . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3.2.1 extest (b[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.2.2 sample/preload (b[3:0] = 0001). . . . . . . . . . . . . . 11-9 11.3.2.3 idcode (b[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.3.2.4 clamp (b[3:0] = 0011) . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.2.5 hi-z (b[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.2.6 enable_once(b[3:0] = 0110) . . . . . . . . . . . . . . . . 11-11 11.3.2.7 debug_request(b[3:0] = 0111) . . . . . . . . . . . . . 11-11 11.3.2.8 bypass (b[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . 11-11 11.4 dsp56300 restrictions . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.5 dsp56309 boundary scan register . . . . . . . . . . . 11-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xvi dsp56309um/d motorola appendix a bootstrap programs . . . . . . . . . . . . . . . . . . a-1 appendix b equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1 i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 host interface (hi08) equates . . . . . . . . . . . . . . . . . b-3 b.3 sci equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.4 essi equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.5 exception processing equates . . . . . . . . . . . . . . . b-7 b.6 timer module equates . . . . . . . . . . . . . . . . . . . . . . . . b-9 b.7 direct memory access (dma) equates . . . . . . . . b-10 b.8 phase-locked loop (pll) equates . . . . . . . . . . . . . b-12 b.9 bus interface unit (biu) equates . . . . . . . . . . . . . b-13 b.10 interrupt equates . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 appendix c dsp56309 bsdl listing . . . . . . . . . . . . . . . . . . . c-1 appendix d programming reference . . . . . . . . . . . . . . . d-1 d.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.1.1 peripheral addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.1.2 interrupt addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.1.3 interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.1.4 programming sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.2 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . . d-4 d.3 interrupt addresses and sources . . . . . . . . . . . d-11 d.4 interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . d-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xvii list of figures figure 1-1 dsp56309 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 figure 2-1 signals identified by functional group . . . . . . . . . . . . . . . . . . . . 2-4 figure 3-1 default settings (0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 figure 3-2 instruction cache enabled (0, 0, 1) . . . . . . . . . . . . . . . . . . . . . . 3-11 figure 3-3 switched program ram (0, 1, 0). . . . . . . . . . . . . . . . . . . . . . . . 3-12 figure 3-4 switched program ram and instruction cache enabled (0, 1, 1)3-13 figure 3-5 16-bit space with default ram (1, 0, 0) . . . . . . . . . . . . . . . . . . 3-14 figure 3-6 16-bit space with instruction cache enabled (1, 0, 1) . . . . . . . 3-15 figure 3-7 16-bit space with switched program ram (1, 1, 0) . . . . . . . . . 3-16 figure 3-8 16-bit space, switched program ram, instruction cache . . . . 3-17 figure 4-1 interrupt priority register c (ipr-c) (x:$ffffff) . . . . . . . . . . 4-13 figure 4-2 interrupt priority register p (ipr-p) (x:$fffffe) . . . . . . . . . . 4-13 figure 4-3 dsp56309 operating mode register (omr) . . . . . . . . . . . . . . 4-17 figure 4-4 pll control (pctl) register. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 figure 4-5 identification register configuration (revision 0) . . . . . . . . . . . 4-19 figure 4-6 address attribute registers (aar0eaar3). . . . . . . . . . . . . . . . 4-20 figure 6-1 hi08 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 figure 6-2 host control register (hcr) (x:$ffffc2). . . . . . . . . . . . . . . . . 6-9 figure 6-3 host status register (hsr) (x:$ffffc3) . . . . . . . . . . . . . . . . 6-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xviii dsp56309um/d motorola figure 6-4 host base address register (hbar) (x:$ffffc5). . . . . . . . . . 6-12 figure 6-5 self chip select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 figure 6-6 host port control register (hpcr) (x:$ffffc4) . . . . . . . . . . . 6-13 figure 6-7 single strobe bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 figure 6-8 dual strobe bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 figure 6-9 host data direction register (hddr) (x:$ffffc8) . . . . . . . . . 6-17 figure 6-10 host data register (hdr) (x:$ffffc9) . . . . . . . . . . . . . . . . . . 6-17 figure 6-11 hsr-hcr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 figure 6-12 interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 figure 6-13 command vector register (cvr) . . . . . . . . . . . . . . . . . . . . . . . 6-25 figure 6-14 interface status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 figure 6-15 interrupt vector register (ivr). . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 figure 6-16 hi08 host request structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 figure 7-1 essi block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 figure 7-2 essi control register a (cra) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 figure 7-3 essi control register b (crb) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 figure 7-4 essi status register (ssisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 figure 7-5 essi transmit slot mask register a (tsma) . . . . . . . . . . . . . . 7-10 figure 7-6 essi transmit slot mask register b (tsmb) . . . . . . . . . . . . . . 7-10 figure 7-7 essi receive slot mask register a (rsma). . . . . . . . . . . . . . . 7-10 figure 7-8 essi receive slot mask register b (rsmb). . . . . . . . . . . . . . . 7-10 figure 7-9 essi clock generator functional block diagram . . . . . . . . . . . 7-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xix figure 7-10 essi frame sync generator functional block diagram. . . . . . 7-13 figure 7-11 crb fsl0 and fsl1 bit operation (fsr = 0) . . . . . . . . . . . . . 7-19 figure 7-12 crb syn bit operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 figure 7-13 crb mod bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 figure 7-14 normal mode, external frame sync (8 bit, 1 word in frame) . 7-22 figure 7-15 network mode, external frame sync (8 bit, 2 words in frame) 7-23 figure 7-16 essi data path programming model (shfd = 0). . . . . . . . . . . 7-31 figure 7-17 essi data path programming model (shfd = 1). . . . . . . . . . . 7-32 figure 7-18 port control register (pcr) (pcrc x:$ffffbf). . . . . . . . . . . 7-44 figure 7-19 port direction register (prr)(prrc x:$ffffbe). . . . . . . . . . 7-44 figure 7-20 port data register (pdr) (pdrc x:$ffffbd) . . . . . . . . . . . . 7-45 figure 8-1 sci control register (scr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 figure 8-2 sci status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 figure 8-3 sci clock control register (sccr) . . . . . . . . . . . . . . . . . . . . . . 8-5 figure 8-4 sci data word formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 figure 8-5 16 x serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 figure 8-6 sci baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 figure 8-7 sci programming model data registers . . . . . . . . . . . . . . . . . 8-19 figure 8-8 port e control register (pcre) . . . . . . . . . . . . . . . . . . . . . . . . 8-27 figure 8-9 port e direction register (prre) . . . . . . . . . . . . . . . . . . . . . . . 8-28 figure 8-10 port e data register (pdre) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 figure 9-1 triple timer module block diagram . . . . . . . . . . . . . . . . . . . . . . 9-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xx dsp56309um/d motorola figure 9-2 timer module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 figure 9-3 timer module programmer?s model . . . . . . . . . . . . . . . . . . . . . . . 9-6 figure 9-4 timer prescaler load register (tplr) . . . . . . . . . . . . . . . . . . . . 9-7 figure 9-5 timer prescaler count register (tpcr) . . . . . . . . . . . . . . . . . . . 9-8 figure 9-6 timer control/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 figure 10-1 once module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 figure 10-2 once module multiprocessor configuration . . . . . . . . . . . . . . . 10-4 figure 10-3 once controller block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-5 figure 10-4 once command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 figure 10-5 once status and control register (oscr). . . . . . . . . . . . . . . . 10-8 figure 10-6 once memory breakpoint logic 0. . . . . . . . . . . . . . . . . . . . . . 10-10 figure 10-7 once breakpoint control register (obcr). . . . . . . . . . . . . . . 10-12 figure 10-8 once trace logic block diagram . . . . . . . . . . . . . . . . . . . . . . 10-15 figure 10-9 once pipeline information and gdb registers . . . . . . . . . . . 10-19 figure 10-10 once trace buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 figure 11-1 tap block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 figure 11-2 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 figure 11-3 jtag instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 figure 11-4 jtag id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 figure 11-5 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 figure d-1 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-15 figure d-2 operating mode register (omr) . . . . . . . . . . . . . . . . . . . . . . . . d-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xxi figure d-3 interrupt priority registerecore (iprec). . . . . . . . . . . . . . . . . . d-17 figure d-4 interrupt priority register e peripherals (iprep). . . . . . . . . . . . d-18 figure d-5 phase-locked loop control register (pctl) . . . . . . . . . . . . . . d-19 figure d-6 host receive and host transmit data registers . . . . . . . . . . . d-20 figure d-7 host control and host status registers . . . . . . . . . . . . . . . . . . d-21 figure d-8 host base address and host port control registers . . . . . . . . d-22 figure d-9 interrupt control and interrupt status registers . . . . . . . . . . . . d-23 figure d-10 interrupt vector and command vector registers . . . . . . . . . . . d-24 figure d-11 host receive and host transmit data registers . . . . . . . . . . . d-25 figure d-12 essi control register a (cra) . . . . . . . . . . . . . . . . . . . . . . . . . d-26 figure d-13 essi control register b (crb) . . . . . . . . . . . . . . . . . . . . . . . . . d-27 figure d-14 essi status register (ssisr). . . . . . . . . . . . . . . . . . . . . . . . . . d-28 figure d-15 essr transmit and receive slot mask registers (tsm, rsm) d-29 figure d-16 sci control register (scr). . . . . . . . . . . . . . . . . . . . . . . . . . . . d-30 figure d-17 sci status and clock control registers (ssr, sccr). . . . . . . d-31 figure d-18 sci receive and transmit data registers (srx, trx) . . . . . . d-32 figure d-19 timer prescaler load/count register (tplr, tpcr). . . . . . . . d-33 figure d-20 timer control/status register (tcsr) . . . . . . . . . . . . . . . . . . . d-34 figure d-21 timer load, compare, count registers (tlr, tcpr, tcr) . . d-35 figure d-22 host data direction and host data registers (hddr, hdr) . . d-36 figure d-23 port c registers (pcrc, prrc, pdrc) . . . . . . . . . . . . . . . . . d-37 figure d-24 port d registers (pcrd, prrd, pdrd) . . . . . . . . . . . . . . . . . d-38 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxii dsp56309um/d motorola figure d-25 port e registers (pcre, prre, pdre) . . . . . . . . . . . . . . . . . d-39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xxiii list of tables table 1-1 high true/low true signal conventions . . . . . . . . . . . . . . . . . . 1-5 table 1-2 on chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 table 2-1 dsp56309 functional signal groupings . . . . . . . . . . . . . . . . . . 2-3 table 2-2 power inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-3 grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-4 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 table 2-5 phase-locked loop signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-6 external address bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 table 2-7 external data bus signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-8 external bus control signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-9 interrupt and mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-10 host port usage considerations . . . . . . . . . . . . . . . . . . . . . . . 2-17 table 2-11 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 table 2-12 enhanced synchronous serial interface 0 (essi0) . . . . . . . . . 2-24 table 2-13 enhanced synchronous serial interface 1 (essi1) . . . . . . . . . 2-28 table 2-14 serial communication interface (sci) . . . . . . . . . . . . . . . . . . . 2-32 table 2-15 triple timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 table 2-16 once/jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 table 3-1 memory space configuration bit settings for the dsp56309 . . . 3-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxiv dsp56309um/d motorola table 3-2 ram configuration bit settings for the dsp56309 . . . . . . . . . . . 3-5 table 3-3 memory space configurations for the dsp56309 . . . . . . . . . . . . 3-7 table 3-4 ram configurations for the dsp56309 . . . . . . . . . . . . . . . . . . . . 3-8 table 3-5 memory locations for program ram and instruction cache . . . . 3-8 table 3-6 memory locations for data ram . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 table 4-1 dsp56309 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 table 4-3 interrupt priority level bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 table 4-4 interrupt source priorities within an ipl . . . . . . . . . . . . . . . . . . 4-14 table 4-5 dma request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 table 6-1 hi08 signal definitions for various operational modes . . . . . . . . 6-6 table 6-2 hi08 data strobe signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 table 6-3 hi08 host request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 table 6-4 host command interrupt priority list . . . . . . . . . . . . . . . . . . . . . 6-10 table 6-5 hdr and hddr functionality . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 table 6-6 dsp side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 table 6-7 host side register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 table 6-8 treq and rreq modes (hdrq = 0) . . . . . . . . . . . . . . . . . . . . 6-23 table 6-9 treq and rreq modes (hdrq = 1) . . . . . . . . . . . . . . . . . . . . 6-23 table 6-10 init command effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 table 6-11 hreq and hdrq settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 table 6-12 host side registers after reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-30 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d xxv table 6-13 hi08 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 table 7-1 essi clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 table 7-2 essi word length selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 table 7-3 fsl1 and fsl0 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 table 7-4 mode and signal definition table . . . . . . . . . . . . . . . . . . . . . . 7-24 table 7-5 port control register and port direction register bits . . . . . . . 7-45 table 8-1 word formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 table 8-2 tcm and rcm bit configuration . . . . . . . . . . . . . . . . . . . . . . . 8-17 table 8-3 sci registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 table 8-4 port control register and port direction register bits . . . . . . . 8-28 table 9-1 prescaler source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 table 9-2 timer control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 table 9-3 inverter (inv) bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 table 10-1 ex bit definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-2 go bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-3 r/w bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-4 once register select encoding . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-5 core status bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 table 10-6 memory breakpoint 0 and 1 select table . . . . . . . . . . . . . . . . 10-12 table 10-7 breakpoint 0 read/write select table . . . . . . . . . . . . . . . . . . 10-13 table 10-8 breakpoint 0 condition select table . . . . . . . . . . . . . . . . . . . 10-13 table 10-9 breakpoint 1 read/write select table . . . . . . . . . . . . . . . . . . 10-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxvi dsp56309um/d motorola table 10-10 breakpoint 1 condition select table . . . . . . . . . . . . . . . . . . . . 10-14 table 10-11 breakpoint 0 and 1 event select table . . . . . . . . . . . . . . . . . . 10-14 table 10-12 tms sequencing for debug_request . . . . . . . . . . . . . . . 10-29 table 10-13 tms sequencing for enable_once . . . . . . . . . . . . . . . . . . 10-30 table 10-14 tms sequencing for reading pipeline registers . . . . . . . . . 10-31 table 11-1 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 table 11-2 dsp56309 bsr bit definitions . . . . . . . . . . . . . . . . . . . . . . . . 11-13 table d-1 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-4 table d-2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-11 table d-3 interrupt source priorities within an ipl . . . . . . . . . . . . . . . . . . d-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 1-1 section 1 dsp56309 overview f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-2 dsp56309um/d motorola dsp56309 overview 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 manual organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 manual conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4 dsp56309 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 dsp56309 core description . . . . . . . . . . . . . . . . . . . . 1-7 1.6 dsp56300 core functional blocks . . . . . . . . . . . . . 1-8 1.7 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.8 dsp56309 block diagram . . . . . . . . . . . . . . . . . . . . . . 1-14 1.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . 1-15 1.10 dsp56309 architecture overview . . . . . . . . . . . . . 1-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview introduction motorola dsp56309um/d 1-3 1.1 introduction this manual describes the dsp56309 24-bit digital signal processor (dsp), its memory, operating modes, and peripheral modules. the dsp56309 is an implementation of the dsp56300 core with a unique configuration of on-chip memory, cache, and peripherals. this manual is intended to be used with the dsp56300 family manual (dsp56300fm/ad), which describes the central processing unit (cpu), core programming models, and instruction set details. dsp56309 technical data (dsp56309/d) provides electrical specifications, timing, pinout, and packaging descriptions of the dsp56309. you can obtain these documents, as well as motorola?s dsp development tools, through a local motorola semiconductor sales office or authorized distributor. to receive the latest information about this dsp, access the motorola dsp home page at the address on the back cover of this document. 1.2 manual organization this manual contains the following sections and appendices: section 1?dsp56309 overview e features list and block diagram e related documentation needed to use this chip e the organization of this manual section 2?signal/connection descriptions e signals on the dsp56309 pins and their functional groupings section 3?memory configuration e dsp56309 memory spaces, ram configuration, memory configuration bit settings, memory configurations, and memory maps section 4?core configuration e registers for configuring the dsp56300 core to program the dsp56309, in particular the interrupt vector locations and the operation of the interrupt priority registers e operating modes and how they affect the processor?s program and data memories f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-4 dsp56309um/d motorola dsp56309 overview manual organization section 5?general-purpose i/o e dsp56309 general-purpose input/output (gpio) capability and the programming model for the gpio signals (operation, registers, and control) section 6?host interface (hi08) e 8-bit host interface (hi08), including a quick reference to the hi08 programming model section 7?enhanced synchronous serial interface (essi) e 24-bit essi, which provides two identical full duplex uart-style serial ports for communications with devices such as codecs, dsps, microprocessors, and peripherals implementing the motorola serial peripheral interface (spi) section 8?serial communication interface (sci) e 24-bit sci, a full duplex serial port for serial communication to dsps, microcontrollers, or other peripherals (such as modems or other rs-232 devices) section 9?triple timer module e the three identical internal timers/event counter devices section 10?on-chip emulation module e the on-chip emulation (oncea) module, which is accessed through the jtag port section 11?jtag port e specifics of the joint test action group (jtag) port on the dsp56309 appendix a?bootstrap programs e bootstrap code used for the dsp56309 appendix b?equates e equates (i/o, hi08, sci, essi, exception processing, timer, dma, pll, biu, and interrupts) for the dsp56309 appendix c?dsp56309 bsdl listing e bsdl listing for the dsp56309 appendix d?programming reference e peripheral addresses, interrupt addresses, and interrupt priorities for the dsp56309 e programming sheets listing the contents of the major dsp56309 registers for programmer?s reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview manual conventions motorola dsp56309um/d 1-5 1.3 manual conventions this manual uses the following conventions: bits within registers are always listed from most significant bit (msb) to least significant bit (lsb). bits within a register are indicated aa[n:m], n>m, when more than one bit is involved in a description. for purposes of description, the bits are presented as if they are contiguous within a register. however, this is not always the case. refer to the programming model diagrams or to the programmer?s sheets to see the exact location of bits within a register. when a bit is described as set, its value is 1. when a bit is described as cleared, its value is 0. the word assert means that a high true (active high) signal is pulled high to v cc or that a low true (active low) signal is pulled low to ground. the word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to v cc . see table 1-1 . pins or signals that are asserted low (made active when pulled to ground) e in text, have an overbar. for example, reset is asserted low. e in code examples, have a tilde in front of their names. in example 1-1 , line 3 refers to the ss0 signal (shown as ~ss0 ). table 1-1 high true/low true signal conventions signal/symbol logic state signal state voltage pin 1 true asserted ground 2 pin false deasserted v cc 3 pin true asserted v cc pin false deasserted ground 1. pin is a generic term for any pin on the chip. 2. ground is an acceptable low voltage level. see the appropriate data sheet for the range of acceptable low voltage levels (typically a ttl logic low). 3. v cc is an acceptable high voltage level. see the appropriate data sheet for the range of acceptable high voltage levels (typically a ttl logic high). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-6 dsp56309um/d motorola dsp56309 overview dsp56309 features sets of signals are indicated by the first and last signals in the set, for instance ha1eha8. code examples are displayed in a monospaced font, as shown in example 1-1 . hex values are indicated with a dollar sign ($) preceding the hex value. for example, $ffffff is the x memory address for the core interrupt priority register (ipr-c). the word ?reset? is used in four different contexts in this manual: e the reset signal, written as reset; e the reset instruction, written as reset; e the reset operating state, written as reset; and e the reset function, written as reset. 1.4 dsp56309 features the dsp56309 is a member of the dsp56300 family of programmable cmos dsps. the dsp56309 uses the dsp56300 core, a high-performance engine with a single clock cycle per instruction. the dsp56300 core provides up to twice the performance of motorola's popular dsp56000 core family, while retaining code compatibility. the dsp56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low-power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products. the dsp56300 core is composed of the data arithmetic logic unit (data alu), address generation unit (agu), program controller (pc), instruction cache controller, bus interface unit, direct memory access (dma) controller, on-chip emulation (once) module, and a pll-based clock oscillator. significant architectural enhancements to the dsp56300 core family include a barrel shifter, 24-bit addressing, an instruction cache, and dma. the dsp56300 core family members contain the dsp56300 core and additional modules. the modules are chosen from a library of standard pre-designed elements, such as memories and peripherals. new modules can be added to the library to meet customer example 1-1 sample code listing bfset #$0007,x:pcc; configure: line 1 ; miso0, mosi0, sck0 for spi master line 2 ; ~ss0 as pc3 for gpio line 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview dsp56309 core description motorola dsp56309um/d 1-7 specifications. a standard interface between the dsp56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. the dsp56309 targets telecommunications applications, such as multi-line voice/data/fax processing, video conferencing, audio applications, control, and general digital signal processing. 1.5 dsp56309 core description the dsp56300 family manual fully describes core features; this manual describes pinout, memory, and peripheral features. 1.5.1 general features 80/100 million instructions per second (mips) with a 80/100 mhz clock at 3.0 - 3.6 v object-code compatible with the dsp56000 core highly parallel instruction set 1.5.2 hardware debugging support on-chip emulation (once ? ) module joint test action group (jtag) test access port (tap) address trace mode reflects internal program ram accesses at the external port 1.5.3 reduced power dissipation very low-power cmos design wait and stop low-power standby modes fully-static logic, operation frequency down to 0 hz (dc) optimized cycle-by-cycle power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-8 dsp56309um/d motorola dsp56309 overview dsp56300 core functional blocks 1.6 dsp56300 core functional blocks the dsp56300 core provides the following functional blocks: data alu agu pcu pll and clock oscillator jtag tap and once module memory in addition, the dsp56309 provides a set of on-chip peripherals, described in section 1.10 . 1.6.1 data alu the data alu performs all the arithmetic and logical operations on data operands in the dsp56300 core. the components of the data alu are as follows: fully pipelined 24 24-bit parallel multiplier-accumulator (mac) bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) conditional alu instructions 24-bit or 16-bit arithmetic support under software control four 24-bit input general-purpose registers: x1, x0, y1, and y0 six data alu registers (a2, a1, a0, b2, b1, and b0) that are concatenated into two general-purpose, 56-bit accumulators, a and b, accumulator shifters two data bus shifter/limiter circuits 1.6.1.1 data alu registers the data alu registers can be read or written over the x data bus (xdb) and the y data bus (ydb) as 16- or 32-bit operands. the source operands for the data alu, which can be 16, 32, or 40 bits, always originate from data alu registers. the results of all data alu operations are stored in an accumulator. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview dsp56300 core functional blocks motorola dsp56309um/d 1-9 all the data alu operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. the destination of every arithmetic operation can be used as a source operand for the immediately following operation without penalty. 1.6.1.2 multiplier-accumulator (mac) the mac unit comprises the main arithmetic processing unit of the dsp56300 core and performs all of the calculations on data operands. for arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form, extension:most significant product:least significant product (ext:msp:lsp). the multiplier executes 24-bit 24-bit, parallel, fractional multiplies between twos-complement signed, unsigned, or mixed operands. the 48-bit product is right-justified and added to the 56-bit contents of either the a or b accumulator. a 56-bit result can be stored as a 24-bit operand. the lsp can either be truncated or rounded into the msp. rounding is performed if specified. 1.6.2 address generation unit (agu) the agu performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses. it implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. the agu operates in parallel with other chip resources to minimize address-generation overhead. the agu is divided into two halves, each with its own address arithmetic logic unit (address alu). each address alu has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. the two address alus are identical. each contains a 16-bit full adder (called an offset adder). a second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. a third full adder (called a reverse-carry adder) is also provided. the offset adder and the reverse-carry adder are in parallel and share common inputs. the only difference between them is that they carry propagates in opposite directions. test logic determines which of the three summed results of the full adders is output. each address alu can update one address register from its respective address register file during one instruction cycle. the contents of the associated modifier register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-10 dsp56309um/d motorola dsp56309 overview dsp56300 core functional blocks specifies the type of arithmetic to be used in the address register update calculation. the modifier value is decoded in the address alu. 1.6.3 program control unit (pcu) the pcu performs instruction prefetch, instruction decoding, hardware do loop control, and exception processing. the pcu implements a seven-stage pipeline and controls the different processing states of the dsp56300 core. the pcu consists of three hardware blocks: program decode controller (pdc) program address generator (pag) program interrupt controller the pdc decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. the pag contains all the hardware needed for program address generation, system stack, and loop control. the pic arbitrates among all interrupt requests (internal interrupts, as well as the five external requests irqa , irqb , irqc , irqd , and nmi ) and generates the appropriate interrupt vector address. pcu features include the following: position independent code (pic) support addressing modes optimized for dsp applications (including immediate offsets) on-chip instruction cache controller on-chip memory-expandable hardware stack nested hardware do loops fast auto-return interrupts the pcu implements its functions using the following registers: pc?program counter register sr?status register la?loop address register lc?loop counter register vba?vector base address register sz?size register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview dsp56300 core functional blocks motorola dsp56309um/d 1-11 sp?stack pointer omr?operating mode register sc?stack counter register the pcu also includes a hardware system stack (ss). 1.6.4 pll and clock oscillator the clock generator in the dsp56300 core is composed of two main blocks: the pll, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator (clkgen), which performs low-power division and clock pulse generation. allows change of low-power divide factor (df) without loss of lock output clock with skew elimination the pll allows the processor to operate at a high internal clock frequency using a low-frequency clock input, a feature that offers two immediate benefits: a lower-frequency clock input reduces the overall electromagnetic interference generated by a system. the ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. 1.6.5 jtag tap and once module the dsp56300 core provides a dedicated user-accessible test access port (tap) that is fully compatible with the ieee 1149.1 standard test access port and boundary scan architecture . problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the dsp56300 core implementation supports circuit-board test strategies based on this standard. the test logic includes a tap consisting of four dedicated signals, a 16-state controller, and three test data registers. a boundary scan register links all device signals into a single shift register. the test logic, implemented utilizing static logic design, is independent of the device system logic. more information on the jtag port is provided in section 11?jtag port . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-12 dsp56309um/d motorola dsp56309 overview dsp56300 core functional blocks the once module provides a means of interacting with the dsp56300 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals. this facilitates hardware and software development on the dsp56300 core processor. once module functions are provided through the jtag tap signals. more information about the once module is provided in section 10?on-chip emulation module . 1.6.6 on-chip memory the memory space of the dsp56300 core is partitioned into program memory space, x data memory space, and y data memory space. the data memory space is divided into x data memory and y data memory in order to work with the two address alus and to feed two operands simultaneously to the data alu. memory space includes internal ram and rom and can be expanded off-chip under software control. more information about the internal memory is provided in section 3?memory configuration . program ram, instruction cache, x data ram, and y data ram size are programmable, as indicated in table 1-2 . table 1-2 on chip memory there is an on-chip 192 x 24-bit bootstrap rom. 1.6.7 off-chip memory expansion memory can be expanded off-chip to do the following: data memory expansion to two 256k 24-bit word memory spaces (or up to two 4 m 24-bit word memory spaces by using the address attribute aa0eaa3 signals) program memory expansion to one 256k 24-bit words memory space (or up to one 4 m 24-bit word memory space by using the address attribute aa0eaa3 signals) additional features of off-chip memory include the following: instruction cache switch mode program ram size instruction cache size x data ram size y data ram size disabled disabled 20k 24-bit 0 7k 24-bit 7k 24-bit enabled disabled 19k 24-bit 1k 24-bit 7k 24-bit 7k 24-bit disabled enabled 24k 24-bit 0 5k 24-bit 5k 24-bit enabled enabled 23k 24-bit 1k 24-bit 5k 24-bit 5k 24-bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview internal buses motorola dsp56309um/d 1-13 external memory expansion port simultaneous glueless interface to static random access memory (sram) and dynamic random access memory (dram) supports interleaved, non-interfering access to both types of memory without losing in-page dram access, including dma-driven access 1.7 internal buses the following buses provide data exchange between the functional blocks of the core: peripheral i/o expansion bus (pio_eb) to peripherals program memory expansion bus (pm_eb) to program ram x memory expansion bus (xm_eb) to x memory y memory expansion bus (ym_eb) to y memory global data bus (gdb) between pcu and other core structures program data bus (pdb) for carrying program data throughout the core x memory data bus (xdb) for carrying x data throughout the core y memory data bus (ydb) for carrying y data throughout the core program address bus (pab) for carrying program memory addresses throughout the core x memory address bus (xab) for carrying x memory addresses throughout the core y memory address bus (yab) for carrying y memory addresses throughout the core all internal buses on the dsp56300 family members are 16-bit buses except the pdb, which is a 24-bit bus. figure 1-1 shows a block diagram of the dsp56309. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-14 dsp56309um/d motorola dsp56309 overview dsp56309 block diagram 1.8 dsp56309 block diagram note: see section 1.6.6 on-chip memory on page 1-12 for details on memory size. figure 1-1 dsp56309 block diagram pll oncea clock generator internal data bus switch program ram ya b xab pa b ydb xdb pdb gdb modc/irqb modb/irqc external data bus switch 13 moda/irqd dsp56300 6 16 24-bit 24 18 x data ram y data ram ddb dab memory expansion area peripheral core ym_eb xm_eb pm_eb pio_eb expansion area 6 sci interface jtag 6 3 reset modd/irqa pinit/nmi 2 boot- strap rom extal xtal address control data triple timer host interface hi08 essi interface address generation unit six channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators 56-bit barrel shifter power mgmt external bus interface & i - cache control external address bus switch aa0456 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview direct memory access (dma) motorola dsp56309um/d 1-15 1.9 direct memory access (dma) the dma block has the following features: six dma channels supporting internal and external accesses one-, two-, and three-dimensional transfers (including circular buffering) end-of-block-transfer interrupts triggering from interrupt lines, all peripherals, and dma channels 1.10 dsp56309 architecture overview the dsp56309 performs a wide variety of fixed-point digital signal processing functions. in addition to the core features previously discussed, the dsp56309 provides the following peripherals: enhanced dsp56000-like 8-bit parallel host interface (hi08) supports a variety of buses (e.g., industry standard architecture) and provides glueless connection to a number of industry standard microcomputers, microprocessors, and dsps two enhanced synchronous serial interfaces (essi0 and essi1), each with one receiver and three transmitters (allows six-channel home theater) serial communications interface (sci) with baud rate generator triple timer module up to 34 programmable general purpose input/output (gpio) pins, depending on which peripherals are enabled 1.10.1 gpio functionality the gpio port consists of as many as thirty-four programmable signals, all of which are also used by the peripherals (hi08, essi, sci, and timer). there are no dedicated gpio signals. peripheral pins are configured as gpio inputs after any reset. (data in the port data register is not affected by a reset.) the gpio functionality for each peripheral is controlled by three memory-mapped registers per peripheral. the techniques for register programming for all gpio functionality is very similar between these interfaces. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-16 dsp56309um/d motorola dsp56309 overview dsp56309 architecture overview 1.10.2 host interface (hi08) the hi08 is a byte-wide, full-duplex, double-buffered, parallel port that can connect directly to the data bus of a host processor. the hi08 supports a variety of buses and connects to a number of industry-standard dsps, microcomputers, and microprocessors without requiring additional logic. the dsp core treats the hi08 as a memory-mapped peripheral occupying eight 24-bit words in data memory space. the dsp can use the hi08 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques. separate transmit and receive data registers are double-buffered to allow the dsp and host processor to transfer data efficiently at high speed. memory mapping allows dsp core communication with the hi08 registers using standard instructions and addressing modes. 1.10.3 enhanced synchronous serial interface (essi) on the dsp56309 are two independent and identical essis. each essi has a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the motorola spi. the essi consists of independent transmitter and receiver sections and a common essi clock generator. the capabilities of the essi include the following: independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs normal mode operation using frame sync network mode operation with as many as 32 time slots programmable word length (8, 12, or 16 bits) program options for frame synchronization and clock generation one receiver and three transmitters per essi allows six-channel home theater 1.10.4 serial communications interface (sci) the dsp56309?s sci provides a full-duplex port for serial communication with other dsps, microprocessors, or peripherals such as modems. the sci interfaces without f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 overview dsp56309 architecture overview motorola dsp56309um/d 1-17 additional logic to peripherals that use ttl-level signals. with a small amount of additional logic, the sci can connect to peripheral interfaces that have non-ttl level signals, such as the rs-232c, rs-422, etc. this interface uses three dedicated signals: transmit data (txd), receive data (rxd), and sci serial clock (sclk). it supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission ( up to 8.25 mbps for a 66 mhz clock). the asynchronous protocols supported by the sci include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. this mode allows the dsp56309 to share a single serial line efficiently with other peripherals. the sci consists of separate transmit and receive sections that can operate asynchronously with respect to each other. a programmable baud-rate generator provides the transmit and receive clocks. an enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general purpose timer when it is not being used by the sci or when the interrupt timing is the same as that used by the sci. 1.10.5 timer module the triple timer module is composed of a common 21-bit prescaler and three independent and identical general-purpose 24-bit timer/event counters, each with its own memory-mapped register set. each timer has a single signal that can function as a gpio signal or as a timer signal. each timer can use internal or external clocking and can interrupt the dsp after a specified number of events (clocks) or can signal an external device after counting internal events. each timer connects to the external world through one bidirectional signal. when this signal is configured as an input, the timer can function as an external event counter or measures external pulse width/signal period. when the signal is used as an output, the timer can function as either a timer, a watchdog, or a pulse width modulator (pwm). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-18 dsp56309um/d motorola dsp56309 overview dsp56309 architecture overview f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 2-1 section 2 signal/connection descriptions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-2 dsp56309um/d motorola signal/connection descriptions 2.1 signal groupings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3 ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.4 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 phase-locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.6 external memory expansion port (port a). . . . . 2-9 2.7 interrupt and mode control . . . . . . . . . . . . . . . . . 2-14 2.8 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.9 enhanced synchronous serial interface . . . . 2-24 2.10 serial communication interface (sci) . . . . . . . . . 2-32 2.11 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.12 once/jtag interface. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions signal groupings motorola dsp56309um/d 2-3 2.1 signal groupings the dsp56309 input and output signals are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . the dsp56309 is operated from a 3 v supply. figure 2-1 is a diagram of dsp56309 signals by functional group. table 2-1 dsp56309 functional signal groupings functional group number of signals detailed description power (v cc )20 table 2-2 ground (gnd) 19 table 2-3 clock 2 table 2-4 pll 3 table 2-5 address bus port a 1 18 table 2-6 data bus 24 table 2-7 bus control 13 table 2-8 interrupt and mode control 5 table 2-9 host interface (hi08) port b 2 16 table 2-11 enhanced synchronous serial interface (essi) ports c and d 3 12 table 2-12 and table 2-13 serial communication interface (sci) port e 4 3 table 2-14 timer 3 table 2-15 once/jtag port 6 table 2-16 note: 1. port a signals define the external memory interface port, including the external address bus, data bus, and control signals. 2. port b signals are the hi08 port signals multiplexed with the gpio signals. 3. port c and d signals are the two essi port signals multiplexed with the gpio signals. 4. port e signals are the sci port signals multiplexed with the gpio signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-4 dsp56309um/d motorola signal/connection descriptions signal groupings fs figure 2-1 signals identified by functional group dsp56309 24 18 timers 3 once/jtag pll core logic i/o address bus data bus bus control hi08 essi/sci/timer a0ea17 d0ed23 tck tdi tdo tms trst de clkout pcap after reset nmi v ccp v ccql v ccqh v cca v ccd v ccc v cch v ccs 4 serial communications interface (sci) 2 4 2 2 gnd p gnd p1 gnd q gnd a gnd d gnd c gnd h gnd s 4 4 2 moda modb modc modd reset non-multiplexed bus h0eh7 ha0 ha1 ha2 hcs/ hcs single ds hrw hds /hds single hr hreq /hreq hack /hack rxd txd sclk sc00esc02 sck0 srd0 std0 tio0 tio1 tio2 8 3 3 2 extal xtal sc10esc12 sck1 srd1 std1 3 multiplexed bus had0ehad7 has /has ha8 ha9 ha10 double ds hrd/ hrd hwr /hwr double hr htrq /htrq hrrq /hrrq port b gpio pb0epb7 pb8 pb9 pb10 pb13 pb11 pb12 pb14 pb15 port e gpio pe0 pe1 pe2 port c gpio pc0epc2 pc3 pc4 pc5 port d gpio pd0epd2 pd3 pd4 pd5 gpio tio0 tio1 tio2 port a aa0601 notes: 1. the hi08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (ds), and single or double host request (hr) configurations. since each of these modes is configured independently, any combination of these modes is possible. these hi08 signals can also be configured alternately as gpio signals (pb0epb15). signals with dual designations (e.g., has /has) have configurable polarity. 2. the essi0, essi1, and sci signals are multiplexed with the port c gpio signals (pc0epc5), port d gpio signals (pd0epd5), and port e gpio signals (pe0epe2), respectively. 3. tio0etio2 can be configured as gpio signals. irqa irqb irqc irqd pinit 3 reset during reset after reset reset during power inputs host interface (h108) 1 enhanced synchronous serial interface (essi0) clock external memory interface pll pll internal logic address bus data bus bus control hi08 essi/sci/timer 4 aa0 eaa3/ ras0 eras3 rd wr ta br bg bb cas bclk bclk enhanced synchronous serial interface (essi1 ) port c port d port e port b grounds pll 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions power motorola dsp56309um/d 2-5 2.2 power power input descriptions for the dsp56309 are listed in table 2-2 . table 2-2 power inputs power name description v ccp pll power ?v ccp is power dedicated for phase-locked loop (pll) use. the voltage should be well regulated, and the input should be provided with an extremely low impedance path to the v cc power rail. v ccp should be bypassed to gnd p by a stabilizing capacitor located as close as possible to the chip package. there is one v ccp input. v ccql (4) quiet core (low) power ?v ccql is an isolated power for the core processing logic. this input must be isolated externally from all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccql inputs. v ccqh (3) quiet external (high) power ?v ccqh is a quiet power source for i/o lines. this input must be tied externally to all other chip power inputs, except v ccql . the user must provide adequate external decoupling capacitors. there are three v ccqh inputs. v cca (3) address bus power ?v cca is an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs except v ccql . the user must provide adequate external decoupling capacitors. there are three v cca inputs. v ccd (4) data bus power ?v ccd is an isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccd inputs. v ccc (2) bus control power ?v ccc is an isolated power for the bus control i/o drivers. this input must be tied externally to all other chip power inputs except v ccql . the user must provide adequate external decoupling capacitors. there are two v ccc inputs. v cch host power ?v cch is an isolated power for the hi08 i/o drivers. this input must be tied externally to all other chip power inputs except v ccql . the user must provide adequate external decoupling capacitors. there is one v cch input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-6 dsp56309um/d motorola signal/connection descriptions ground 2.3 ground ground descriptions for the dsp56309 are listed in table 2-3 . v ccs (2) essi, sci, and timer power ?v ccs is an isolated power for the essi, sci, and timer i/o drivers. this input must be tied externally to all other chip power inputs except v ccql . the user must provide adequate external decoupling capacitors. there are two v ccs inputs. note: these designations are package-dependent. some packages connect all v cc inputs except v ccp to each other internally. on those packages, all power input, except v ccp , are labeled v cc . the number of connections indicated in this table are minimum values; the total v cc connections are package-dependent. table 2-3 grounds ground name description gnd p pll ground ?gnd p is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 m f capacitor located as close as possible to the chip package. there is one gnd p connection. gnd p1 pll ground 1 ?gnd p1 is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. there is one gnd p1 connection. gnd q (4) quiet ground ?gnd q is an isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are four gnd q connections. gnd a (4) address bus ground ?gnd a is an isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are four gnd a connections. table 2-2 power inputs (continued) power name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions clock motorola dsp56309um/d 2-7 2.4 clock clock signal descriptions for the dsp56309 are listed in table 2-4 . gnd d (4) data bus ground ?gnd d is an isolated ground for sections of the data bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are four gnd d connections. gnd c (2) bus control ground ?gnd c is an isolated ground for the bus control i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are two gnd c connections. gnd h host ground ?gnd h is an isolated ground for the hi08 i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there is one gnd h connection. gnd s (2) essi, sci, and timer ground ?gnd s is an isolated ground for the essi, sci, and timer i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are two gnd s connections. note: these designations are package-dependent. some packages connect all gnd inputs, except gnd p and gnd p1 , to each other internally. on those packages, all ground connections, except gnd p and gnd p1 , are labeled gnd. the number of connections indicated in this table are minimum values; the total gnd connections are package-dependent. table 2-4 clock signals signal name type state during reset signal description extal input input external clock/crystal input ?extal interfaces the internal crystal oscillator input to an external crystal or an external clock. table 2-3 grounds (continued) ground name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-8 dsp56309um/d motorola signal/connection descriptions phase-locked loop (pll) 2.5 phase-locked loop (pll) phase-locked loop signal descriptions are listed in table 2-5 . xtal output chip-driven crystal output ?xtal connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. table 2-5 phase-locked loop signals signal name type state during reset signal description pcap input input pll capacitor ?pcap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap can be tied to v cc , tied to gnd, or left floating. clkout output chip-driven clock output ?clkout provides an output clock synchronized to the internal core clock phase. if the pll is enabled and both the multiplication and division factors equal one, then clkout is also synchronized to extal. if the pll is disabled, the clkout frequency is half the frequency of extal. table 2-4 clock signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions external memory expansion port (port a) motorola dsp56309um/d 2-9 2.6 external memory expansion port (port a) when the dsp56309 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port a signals: a0ea17, d0ed23, aa0/ras0 eaa3/ras3 , rd , wr , bb , cas , bclk, bclk . 2.6.1 external address bus external address bus signals for the dsp56309 are listed in table 2-6 . pinit/ nmi input input pll initial/non-maskable interrupt ?during assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is enabled or disabled. after reset deassertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered non-maskable interrupt (nmi) request internally synchronized to clkout. table 2-6 external address bus signals signal name type state during reset signal description a0ea17 output tri-stated address bus ?when the dsp is the bus master, a0ea17 are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power dissipation, a0ea17 do not change state when external memory spaces are not being accessed. table 2-5 phase-locked loop signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-10 dsp56309um/d motorola signal/connection descriptions external memory expansion port (port a) 2.6.2 external data bus external data bus signals for the dsp56309 are listed in table 2-7 . 2.6.3 external bus control external bus control signal descriptions for the dsp56309 are listed in table 2-8 . table 2-7 external data bus signals signal name type state during reset signal description d0ed23 input/ output weakly driven by bus keeper data bus ?when the dsp is the bus master, d0ed23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. otherwise, d0ed23 are weakly driven by the bus keeper. table 2-8 external bus control signals signal name type state during reset signal description aa0e aa3/ ras0 e ras3 output tri-stated address attribute or row address strobe ?when defined as aa, these signals can be used as chip selects or additional address lines. when defined as ras , these signals can be used as ras for dram interface. these signals are tri-statable outputs with programmable polarity. rd output tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d0ed23). otherwise, rd is tri-stated. wr output tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d0ed23). otherwise, the signals are tri-stated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions external memory expansion port (port a) motorola dsp56309um/d 2-11 ta input ignored input transfer acknowledge ?if the dsp56309 is the bus master and there is no external bus activity, or the dsp56309 is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle indefinitely. any number of wait states (1, 2,..., infinity) can be added to the wait states inserted by the bcr by keeping ta deasserted. in typical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to clkout. the number of wait states is determined by the ta input or by the bcr, whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. in order to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait state access cannot be extended by ta deassertion; otherwise, improper operation can result. ta can operate synchronously or asynchronously depending on the setting of the tas bit in the omr. you must not use ta functionality while performing dram type accesses; otherwise, improper operation can result. table 2-8 external bus control signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-12 dsp56309um/d motorola signal/connection descriptions external memory expansion port (port a) br output output (deasserted) bus request ?br is an active-low output, never tri-stated. br is asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br can be asserted or deasserted independent of whether the dsp56309 is a bus master or a bus slave. bus parking allows br to be deasserted even though the dsp56309 is the bus master; see the description of bus parking in the bb signal description. the bus request hole (brh) bit in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. br is only affected by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. bg input ignored input bus grant ?bg is an active-low input. bg must be asserted/deasserted synchronous to clkout for proper operation. bg is asserted by an external bus arbitration circuit when the dsp56309 becomes the next bus master. when bg is asserted, the dsp56309 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this can occur in the middle of an instruction that requires more than one external bus cycle for execution. table 2-8 external bus control signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions external memory expansion port (port a) motorola dsp56309um/d 2-13 bb input/ output input bus busy ?bb is a bidirectional active-low input/output and must be asserted and deasserted synchronous to clkout. bb indicates that the bus is active. only after bb is deasserted can the pending bus master become the bus master (and then assert the signal again). the bus master can keep bb asserted after ceasing bus activity regardless of whether br is asserted or deasserted. this is called bus parking and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. the deassertion of bb is done by an active pull-up method (i.e., bb is driven high and then released and held high by an external pull-up resistor). bb requires an external pull-up resistor. cas output tri-stated column address strobe ?when the dsp is the bus master, cas is an active-low output used by dram to strobe the column address. otherwise, if the bus mastership enable (bme) bit in the dram control register is cleared, the signal is tri-stated. bclk output tri-stated bus clock ?when the dsp is the bus master, bclk is an active-high output. bclk is active as a sampling signal when the program address tracing mode is enabled (by setting the ate bit in the omr). when bclk is active and synchronized to clkout by the internal pll, bclk precedes clkout by 1/4 of a clock cycle. the bclk rising edge can be used to sample the internal program memory access on the a0ea23 address lines. bclk output tri-stated bus clock not ?when the dsp is the bus master, bclk is an active-low output and is the inverse of the bclk signal. otherwise, the signal is tri-stated. table 2-8 external bus control signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-14 dsp56309um/d motorola signal/connection descriptions interrupt and mode control 2.7 interrupt and mode control the interrupt and mode control signals select the chip?s operating mode as it comes out of hardware reset. after reset is deasserted, these inputs are hardware interrupt request lines. table 2-9 interrupt and mode control signal name type state during reset signal description reset input input reset? reset is an active-low, schmitt-trigger input. deassertion of reset is internally synchronized to the clock out (clkout). when asserted, the chip is placed in the reset state and the internal phase generator is reset. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. if reset is deasserted synchronous to clkout, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in lock-step. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted after power up. moda irqa input input mode select a ?moda is an active-low schmitt-trigger input, internally synchronized to clkout. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the omr when the reset signal is deasserted. external interrupt request a?after reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if irqa is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqa to exit the wait state. if the processor is in the stop standby state and irqa is asserted, the processor exits the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions interrupt and mode control motorola dsp56309um/d 2-15 modb irqb input input mode select b? modb is an active-low schmitt-trigger input, internally synchronized to clkout. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. external interrupt request b ?after hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if irqb is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqb to exit the wait state. modc irqc input input mode select c? modc is an active-low schmitt-trigger input, internally synchronized to clkout. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. external interrupt request c ?after hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if irqc is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqc to exit the wait state. table 2-9 interrupt and mode control (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-16 dsp56309um/d motorola signal/connection descriptions host interface (hi08) 2.8 host interface (hi08) the hi08 provides a fast parallel 8-bit port, which can connect directly to the host bus. the hi08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, dsps, and dma hardware. 2.8.1 host port usage considerations when reading multiple-bit registers that are written by another asynchronous system, you must synchronize carefully. this problem commonly occurs when two asynchronous systems are connected (as they are in the host port). the considerations for proper operation are discussed in table 2-10 . modd irqd input input mode select d ?modd is an active-low schmitt-trigger input, internally synchronized to clkout. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. external interrupt request d ?after hardware reset, this signal becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if irqd is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqd to exit the wait state. table 2-9 interrupt and mode control (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions host interface (hi08) motorola dsp56309um/d 2-17 2.8.2 host port configuration the functions of the signals associated with the hi08 vary according to the programmed configuration of the interface as determined by the hi08 port control register (hpcr). refer to section 6?host interface (hi08) for detailed descriptions of this and the other configuration registers used with the hi08. host interface signal descriptions for the dsp56309 are listed in table 2-11 . table 2-10 host port usage considerations action description asynchronous read of receive byte registers when reading the receive byte registers, receive register high (rxh), receive register middle (rxm), or receive register low (rxl), use interrupts or poll the receive register data full (rxdf) flag which indicates that data is available. this assures that the data in the receive byte registers is valid. asynchronous write to transmit byte registers do not write to the transmit byte registers, transmit register high (txh), transmit register middle (txm), or transmit register low (txl), unless the transmit register data empty (txde) bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers transfer valid data to the host receive (hrx) register. asynchronous write to host vector change the host vector (hv) register only when the host command bit (hc) is clear. this guarantees that the dsp interrupt control logic receives a stable vector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-18 dsp56309um/d motorola signal/connection descriptions host interface (hi08) table 2-11 host interface signal name type state during reset signal description h0eh7 had0e had7 pb0epb7 input/ output input/ output input or output tri-stated host data ?when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, these signals are lines 0e7 of the data bidirectional, tri-state bus. host address? when hi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0e7 of the address/data bidirectional, multiplexed, tri-state bus. port b 0e7 ?when the hi08 is configured as gpio through the hpcr, these signals are individually programmed as inputs or outputs through the hi08 data direction register (hddr). ha0 has /has pb8 input input input or output input host address input 0 ?when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus. host address strobe? when hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programmable but is configured active-low (has ) following reset. port b 8 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions host interface (hi08) motorola dsp56309um/d 2-19 ha1 ha8 pb9 input input input or output input host address input 1 ?when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 1 of the host address (ha1) input bus. host address 8 ?when hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 8 of the host address (ha8) input bus. port b 9 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. ha2 ha9 pb10 input input input or output input host address input 2 ?when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 2 of the host address (ha2) input bus. host address 9 ?when hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 9 of the host address (ha9) input bus. port b 10 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. table 2-11 host interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-20 dsp56309um/d motorola signal/connection descriptions host interface (hi08) hrw hrd /hrd pb11 input input input or output input host read/write ?when hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host read/write (hrw) input. host read data ?when hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host read data strobe (hrd) schmitt-trigger input. the polarity of the data strobe is programmable, but is configured as active-low (hrd ) after reset. port b 11 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. hds /hds hwr / hwr pb12 input input input or output input host data strobe? when hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host data strobe (hds) schmitt-trigger input. the polarity of the data strobe is programmable, but is configured as active-low (hds ) following reset. host write data ?when hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host write data strobe (hwr) schmitt-trigger input. the polarity of the data strobe is programmable, but is configured as active-low (hwr ) following reset. port b 12 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. table 2-11 host interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions host interface (hi08) motorola dsp56309um/d 2-21 hcs ha10 pb13 input input input or output input host chip select? when hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable, but is configured active-low (hcs ) after reset. host address 10 ?when hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 10 of the host address (ha10) input bus. port b 13 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. table 2-11 host interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-22 dsp56309um/d motorola signal/connection descriptions host interface (hi08) hreq / hreq htrq / htrq pb14 output output input or output input host request ?when hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request (hreq) output. the polarity of the host request is programmable, but is configured as active-low (hreq ) following reset. the host request can be programmed as a driven or open-drain output. transmit host request? when hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the transmit host request (htrq) output. the polarity of the host request is programmable, but is configured as active-low (htrq ) following reset. the host request can be programmed as a driven or open-drain output. port b 14 ?when the hi08 is programmed to interface a multiplexed host bus and the signal is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. table 2-11 host interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions host interface (hi08) motorola dsp56309um/d 2-23 hack / hack hrrq / hrrq pb15 input output input or output input host acknowledge ?when hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host acknowledge (hack) schmitt-trigger input. the polarity of the host acknowledge is programmable, but is configured as active-low (hack ) after reset. receive host request ?when hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the receive host request (hrrq) output. the polarity of the host request is programmable, but is configured as active-low (hrrq ) after reset. the host request can be programmed as a driven or open-drain output. port b 15 ?when the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. table 2-11 host interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-24 dsp56309um/d motorola signal/connection descriptions enhanced synchronous serial interface 2.9 enhanced synchronous serial interface two synchronous serial interfaces (essi0 and essi1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals which implement the motorola spi. 2.9.1 essi0 the essi0 signal descriptions for the dsp56309 are listed in table 2-12 . table 2-12 enhanced synchronous serial interface 0 (essi0) signal name type state during reset signal description sc00 pc0 input or output input serial control 0 ?the function of sc00 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. this signal is driven by a weak keeper after reset. port c 0 ?the default configuration following reset is gpio input pc0. when this port is configured as pc0, signal direction is controlled through the port c direction register (prr0). the signal can be configured as essi signal sc00 through the port c control register (pcr0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions enhanced synchronous serial interface motorola dsp56309um/d 2-25 sc01 pc1 input/ output input or output input serial control 1 ?the function of this signal is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. this signal is driven by a weak keeper after reset. port c 1 ?the default configuration following reset is gpio input pc1. when this port is configured as pc1, signal direction is controlled through prr0. the signal can be configured as an essi signal sc01 through pcr0. sc02 pc2 input/ output input or output input serial control signal 2 ?sc02 is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). this signal is driven by a weak keeper after reset. port c 2 ?the default configuration following reset is gpio input pc2. when this port is configured as pc2, signal direction is controlled through prr0. the signal can be configured as an essi signal sc02 through pcr0. table 2-12 enhanced synchronous serial interface 0 (essi0) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-26 dsp56309um/d motorola signal/connection descriptions enhanced synchronous serial interface sck0 pc3 input/ output input or output input serial clock ?sck0 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the essi interface. the sck0 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6 t (i.e., the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. this signal is driven by a weak keeper after reset. port c 3 ?the default configuration following reset is gpio input pc3. when this port is configured as pc3, signal direction is controlled through prr0. the signal can be configured as an essi signal sck0 through pcr0. srd0 pc4 input/ output input or output input serial receive data ?srd0 receives serial data and transfers the data to the essi receive shift register. srd0 is an input when data is being received. this signal is driven by a weak keeper after reset. port c 4 ?the default configuration following reset is gpio input pc4. when this port is configured as pc4, signal direction is controlled through prr0. the signal can be configured as an essi signal srd0 through pcr0. table 2-12 enhanced synchronous serial interface 0 (essi0) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions enhanced synchronous serial interface motorola dsp56309um/d 2-27 2.9.2 essi1 the essi1 signal descriptions for the dsp56309 are listed in table 2-13 . std0 pc5 input/ output input or output input serial transmit data ?std0 is used for transmitting data from the serial transmit shift register. std0 is an output when data is being transmitted. this signal is driven by a weak keeper after reset. port c 5 ?the default configuration following reset is gpio input pc5. when this port is configured as pc5, signal direction is controlled through prr0. the signal can be configured as an essi signal std0 through pcr0. table 2-12 enhanced synchronous serial interface 0 (essi0) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-28 dsp56309um/d motorola signal/connection descriptions enhanced synchronous serial interface table 2-13 enhanced synchronous serial interface 1 (essi1) signal name type state during reset signal description sc10 pd0 input or output input serial control 0 ?the function of sc10 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. this signal is driven by a weak keeper after reset. port d 0 ?the default configuration following reset is gpio input pd0. when this port is configured as pd0, signal direction is controlled through the port d direction register (prr1). the signal can be configured as an essi signal sc10 through the port d control register (pcr1). sc11 pd1 input/ output input or output input serial control 1 ?the function of this signal is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. this signal is driven by a weak keeper after reset. port d 1 ?the default configuration following reset is gpio input pd1. when this port is configured as pd1, signal direction is controlled through prr1. the signal can be configured as an essi signal sc11 through pcr1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions enhanced synchronous serial interface motorola dsp56309um/d 2-29 sc12 pd2 input/ output input or output input serial control signal 2 ?sc12 is used for frame sync i/o. sc12 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter. the receiver receives an external frame sync signal as well when in synchronous operation). this signal is driven by a weak keeper after reset. port d 2 ?the default configuration following reset is gpio input pd2. when this port is configured as pd2, signal direction is controlled through prr1. the signal can be configured as an essi signal sc12 through pcr1. table 2-13 enhanced synchronous serial interface 1 (essi1) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-30 dsp56309um/d motorola signal/connection descriptions enhanced synchronous serial interface sck1 pd3 input/ output input or output input serial clock ?sck1 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the essi interface. the sck1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. this signal is driven by a weak keeper after reset. port d 3 ?the default configuration following reset is gpio input pd3. when this port is configured as pd3, signal direction is controlled through prr1. the signal can be configured as an essi signal sck1 through pcr1. srd1 pd4 input/ output input or output input serial receive data ?srd1 receives serial data and transfers the data to the essi receive shift register. srd1 is an input when data is being received. this signal is driven by a weak keeper after reset. port d 4 ?the default configuration following reset is gpio input pd4. when this port is configured as pd4, signal direction is controlled through prr1. the signal can be configured as an essi signal srd1 through pcr1. table 2-13 enhanced synchronous serial interface 1 (essi1) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions enhanced synchronous serial interface motorola dsp56309um/d 2-31 std1 pd5 input/ output input or output input serial transmit data ?std1 is used for transmitting data from the serial transmit shift register. std1 is an output when data is being transmitted. this signal is driven by a weak keeper after reset. port d 5 ?the default configuration following reset is gpio input pd5. when this port is configured as pd5, signal direction is controlled through prr1. the signal can be configured as an essi signal std1 through pcr1. table 2-13 enhanced synchronous serial interface 1 (essi1) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-32 dsp56309um/d motorola signal/connection descriptions serial communication interface (sci) 2.10 serial communication interface (sci) sci provides a full duplex port for serial communication to other dsps, microprocessors, or peripherals such as modems. sci signal descriptions are listed in table 2-14 . table 2-14 serial communication interface (sci) signal name type state during reset signal description rxd pe0 input input or output input serial receive data ?this input receives byte oriented serial data and transfers it to the sci receive shift register. this signal is driven by a weak keeper after reset. port e 0 ?the default configuration following reset is gpio input pe0. when this port is configured as pe0, signal direction is controlled through the sci port e direction register (prr). the signal can be configured as an sci signal rxd through the sci port e control register (pcr). txd pe1 output input or output input serial transmit data ?this signal transmits data from sci transmit data register. this signal is driven by a weak keeper after reset. port e 1 ?the default configuration following reset is gpio input pe1. when this port is configured as pe1, signal direction is controlled through the sci prr. the signal can be configured as an sci signal txd through the sci pcr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions timers motorola dsp56309um/d 2-33 2.11 timers three identical and independent timers are implemented in the dsp56309. each timer can use internal or external clocking; each timer can interrupt the dsp56309 after a specified number of events (clocks) or can signal an external device after counting a specific number of internal events. triple timer signal descriptions are listed in table 2-15 . sclk pe2 input/ output input or output input serial clock ?this is the bidirectional schmitt-trigger input signal providing the input or output clock used by the transmitter and/or the receiver. this signal is driven by a weak keeper after reset. port e 2 ?the default configuration following reset is gpio input pe2. when this port is configured as pe2, signal direction is controlled through the sci prr. the signal can be configured as an sci signal sclk through the sci pcr. table 2-14 serial communication interface (sci) (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-34 dsp56309um/d motorola signal/connection descriptions timers table 2-15 triple timer signals signal name type state during reset signal description tio0 input or output input timer 0 schmitt-trigger input/output ? when timer 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. this signal is driven by a weak keeper after reset. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 0 control/status register (tcsr0). tio1 input or output input timer 1 schmitt-trigger input/output ? when timer 1 functions as an external event counter or in measurement mode, tio1 is used as input. when timer 1 functions in watchdog, timer, or pulse modulation mode, tio1 is used as output. this signal is driven by a weak keeper after reset. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 1 control/status register (tcsr1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions once/jtag interface motorola dsp56309um/d 2-35 2.12 once/jtag interface once/jtag interface signal descriptions are listed in table 2-16 . tio2 input or output input timer 2 schmitt-trigger input/output ? when timer 2 functions as an external event counter or in measurement mode, tio2 is used as input. when timer 2 functions in watchdog, timer, or pulse modulation mode, tio2 is used as output. this signal is driven by a weak keeper after reset. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 2 control/status register (tcsr2). table 2-16 once/jtag interface signal name type state during reset signal description tck input input test clock ?tck is a test clock input signal used to synchronize the jtag test logic. its pin has a pull-up resistor. tdi input input test data input ?tdi is a test data serial input signal used for test instructions and data. tdi is sampled on the rising edge of tck and has an internal pull-up resistor. table 2-15 triple timer signals (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-36 dsp56309um/d motorola signal/connection descriptions once/jtag interface tdo output tri-stated test data output ?tdo is a test data serial output signal used for test instructions and data. tdo is tri-statable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select ?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. trst input input test reset ?trst is an active-low schmitt-trigger input signal used to asynchronously initialize the test controller. trst has an internal pull-up resistor. trst must be asserted after power up. table 2-16 once/jtag interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions once/jtag interface motorola dsp56309um/d 2-37 de input/ output input debug event ?de is an open-drain, bidirectional, active-low signal providing, as an input, a means of entering debug mode of operation from an external command controller, and as an output, a means of acknowledging that the chip has entered debug mode. this signal, when asserted as an input, causes the dsp56300 core to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the debug serial input line. this signal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition. the de has an internal pull-up resistor. this is not a standard part of the jtag tap controller. the signal connects directly to the once module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode. all other interfacing with the once module must occur through the jtag port. table 2-16 once/jtag interface (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-38 dsp56309um/d motorola signal/connection descriptions once/jtag interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 3-1 section 3 memory configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-2 dsp56309um/d motorola memory configuration 3.1 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 ram configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 memory configurations . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . 3-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory spaces motorola dsp56309um/d 3-3 3.1 memory spaces the dsp56309 provides three independent memory spaces: program x data y data each memory space uses 24-bit addressing by default. the program and data word length is 24 bits. moreover, this device supports remapping address attribute registers on the fly, thus allowing access to 16 m of memory. the dsp56309 provides a sixteen-bit compatibility mode that effectively uses 16-bit addressing for each memory space, allowing access to 64k each of memory. this mode puts zeroes in the most significant byte of the usual (24-bit) program and data word; it ignores the zeroed byte, thus effectively using 16-bit program and data words. the sixteen-bit compatibility mode allows the dsp56309 to use 56000 object code without change, thus minimizing system cost for applications that use the smaller address space. see the dsp56300 family manual for further information. 3.1.1 program memory space program memory space consists of the following: internal program memory (program ram, 20k by default) bootstrap program rom (192 x 24-bit) (optionally) off-chip memory expansion (as much as 16 m in 24-bit mode and 64k in 16-bit mode) (optionally) instruction cache (1k) formed from program ram program memory space at locations $ff00c0 to $ffffff is reserved and should not be accessed. 3.1.2 data memory spaces data memory space is divided into x data memory and y data memory to match the natural partitioning of dsp algorithms. the data memory partitioning allows the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-4 dsp56309um/d motorola memory configuration memory spaces dsp56309 to feed two operands to the data alu simultaneously, enabling it to perform a multiply-accumulate operation in one clock cycle. x and y data memory are identical in structure and functionality except for the upper 128 words of each space. the upper 128 words of x data memory are reserved for internal i/o. we recommend that the programmer reserve the upper 128 words of y data memory for external i/o. (for further information, see section 3.1.2.1 x data memory space and section 3.1.2.2 y data memory space .) x and y data memory space each consist of the following: internal data memory (x data ram and y data ram, the default size of each is 7k, but they can be switched to 5k each) (optionally) off-chip memory expansion (up to 16 m in the 24-bit address mode and 64k in the 16-bit address mode) 3.1.2.1 x data memory space the on-chip peripheral registers and some of the dsp56309 core registers occupy the top 128 locations of x data memory ($ffff80e$ffffff in the 24-bit address mode or $ff80e$ffff in the 16-bit address mode). this area is called x-i/o space, and it can be accessed by move and movep instructions and by bit oriented instructions (bchg, bclr, bset, btst, brclr, brset, bsclr, bsset, jclr, jset, jsclr, and jsset). for a listing of the contents of this area, see the programming sheets in appendix d?programming reference . the x memory space at locations $ff0000 to $ffefff is reserved and should not be accessed by the programmer. 3.1.2.2 y data memory space the off-chip peripheral registers should be mapped into the top 128 locations of y data memory ($ffff80e$ffffff in the 24-bit address mode or $ff80e$ffff in the 16-bit address mode) to take advantage of the move peripheral data (movep) instruction and the bit oriented instructions (bchg, bclr, bset, btst, brclr, brset, bsclr, bsset, jclr, jset, jsclr, and jsset). the y memory space at locations $ff0000 to $ffefff is reserved and should not be accessed by the programmer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration ram configuration motorola dsp56309um/d 3-5 3.1.3 memory space configuration memory space addressing is 24-bit by default. the dsp56309 switches to sixteen-bit address compatibility mode by setting the sixteen-bit compatibility (sc) bit in the status register (sr). memory maps for the different configurations are shown in figure 3-1 through figure 3-8 . 3.2 ram configuration the dsp56309 contains 34k of ram, divided by default into the following: program ram (20k) x data ram (7k) y data ram (7k) ram configuration depends on two bits: the cache enable (ce) of the sr and the memory select (ms) of the operating mode register (omr). table 3-1 memory space configuration bit settings for the dsp56309 bit abbreviation bit name bit location cleared = 0 effect (default) set = 1 effect sc sixteen-bit compatibility sr 13 16m word address space (24-bit address) 64k word address space (16-bit address) table 3-2 ram configuration bit settings for the dsp56309 bit abbreviation bit name bit location cleared = 0 effect (default) set = 1 effect ce cache enable sr 19 cache disabled cache enabled 1k ms memory switch omr 7 program ram 20k x data ram 7k y data ram 7k program ram 24k x data ram 5k y data ram 5k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-6 dsp56309um/d motorola memory configuration ram configuration memory maps for the different configurations are shown in figure 3-1 through figure 3-8 . note: the ms bit cannot be changed when ce is set. the instruction cache occupies the top 1k of what would otherwise be program ram; if you switch memory into or out of program ram when the cache is enabled, the switch causes conflicts. to change the ms bit when ce is set, do the following: 1. clear ce. 2. change ms. 3. set ce. 3.2.1 on-chip program memory (program ram) the on-chip program ram consists of 24-bit wide, high-speed, internal static ram occupying the lowest 20k (default), 23k, 24k, or 19k locations in the program memory space (depending on the settings of the ms and ce bits). the program ram default organization is 80 banks of 256 24-bit words (20k). the upper eight banks of both x data ram and y data ram can be configured as program ram by setting the ms bit. when the ce is set, the upper 1k of program ram is used as an internal instruction cache. caution while the contents of program ram are unaffected by toggling the ms bit, the location of program data placed in the program ram/instruction cache area changes after the ms bit is toggled, since the cache always occupies the top-most 1k program ram addresses. to preserve program data integrity, do not set or clear the ms bit when the ce bit is set. see section 3.2 on page 3-5 for the correct procedure. 3.2.2 on-chip x data memory (x data ram) the on-chip x data ram consists of 24-bit wide, high-speed, internal static ram occupying the lowest 7k (default) or 5k locations in the x memory space. the size of the x data ram depends on the setting of the ms bit (default: ms is cleared). the x data ram default organization is 28 banks of 256 (7k) 24-bit words. eight banks of ram can be switched from the x data ram to the program ram by setting the ms bit (leaving 5k of x data ram). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory configurations motorola dsp56309um/d 3-7 3.2.3 on-chip y data memory (y data ram) the on-chip y data ram consists of 24-bit wide, high-speed, internal static ram occupying the lowest 7k (default) or 5k locations in the y memory space. the size of the y data ram is dependent on the setting of the ms bit (default: ms is cleared). the y data ram default organization is 28 banks of 256 (7k) 24-bit words. eight banks of ram can be switched from the y data ram to the program ram by setting the ms bit (leaving 5k of y data ram). 3.2.4 bootstrap rom the bootstrap code is accessed at addresses $ff0000 to $fff0bf (192 words) in program memory space. the bootstrap rom cannot be accessed in 16-bit address compatibility mode. see appendix a?bootstrap programs for a complete listing of the bootstrap code. 3.3 memory configurations memory configuration determines the size and address range for addressable memory, as well as the amount of memory allocated to program ram, data ram, and the instruction cache. 3.3.1 memory space configurations the memory space configurations are listed in table 3-3 . table 3-3 memory space configurations for the dsp56309 sc bit setting addressable memory size address range number of address bits 0 16m words $000000e $ffffff 24 1 64k words $0000e$ffff 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-8 dsp56309um/d motorola memory configuration memory configurations 3.3.2 ram configurations the ram configurations for the dsp56309 appear in table 3-4 . the actual memory locations for program ram and the instruction cache in the program memory space are determined by the ms and ce bits. their addresses appear in table 3-5 . table 3-4 ram configurations for the dsp56309 bit settings memory sizes (in k) ms ce program ram x data ram y data ram cache 0020770 0119771 1024550 1123551 table 3-5 memory locations for program ram and instruction cache ms ce program ram location cache location 0 0 $0000e$4fff n/a 0 1 $0000e$4bff $4c00e$4fff 1 0 $0000e$5fff n/a 1 1 $0000e$5bff $5c00e$5fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory maps motorola dsp56309um/d 3-9 the actual memory locations for both x and y data ram in their own memory space are determined by the ms bit. their addresses appear in table 3-6 . 3.4 memory maps figure 3-1 through figure 3-8 illustrate each of the memory space and ram configurations defined by the settings of the sc, ms, and ce bits. the figures show the configuration, and the accompanying tables show the bit settings, memory sizes, and memory locations. table 3-6 memory locations for data ram ms data ram location 0 $0000e$1bff 1 $0000e$13ff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-10 dsp56309um/d motorola memory configuration memory maps figure 3-1 default settings (0, 0, 0) aa0557 internal reserved bootstrap rom external internal program ram 20k $ffffff $fff0c0 $ff0000 $005000 $000000 internal reserved internal i/o external internal x data ram 7k external $001c00 internal reserved external i/o external internal y data ram 7k external $ff0000 $000000 $fff000 $ffff80 program x data y data bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 000 20k $0000e$4fff 7k $0000e$1bff 7k $0000e$1bff none 16m $ffffff $001c00 $ff0000 $000000 $fff000 $ffff80 $ffffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory maps motorola dsp56309um/d 3-11 figure 3-2 instruction cache enabled (0, 0, 1) aa0561 internal reserved bootstrap rom external internal program ram 19k $ffffff $fff0c0 $ff0000 $005000 $000000 internal reserved internal i/o external internal x data ram 7k external $001c00 internal reserved external i/o external internal y data ram 7k external $fff000 $ffff80 program x data y data i-cache 1k $004c00 bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 001 19k $0000e $4bff 7k $0000e $1bff 7k $0000e $1bff 1k $4c00e $4fff 16 m $ffffff $ff0000 $000000 $001c00 $fff000 $ffff80 $ffffff $ff0000 $000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-12 dsp56309um/d motorola memory configuration memory maps figure 3-3 switched program ram (0, 1, 0) internal reserved bootstrap rom internal program ram 24k $ffffff $fff0c0 $ff0000 $000000 internal reserved internal i/o external internal x data ram 5k external $001400 internal reserved external i/o external internal y data ram 5k external $fff000 $ffff80 program x data y data bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 010 24k $0000e $5fff 5k $0000e $13ff 5k $0000e $13ff none 16 m aa0559 external $ffffff $ff0000 $000000 $001400 $fff000 $ffff80 $ffffff $ff0000 $000000 $006000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory maps motorola dsp56309um/d 3-13 figure 3-4 switched program ram and instruction cache enabled (0, 1, 1) aa0563 internal reserved bootstrap rom external internal ram 23k $ffffff $fff0c0 $ff0000 $000000 internal reserved internal i/o external internal x data ram 5k external $001400 internal reserved external i/o external internal y data ram 5k external $fff000 $ffff80 program x data y data i-cache 1k $006000 $005c00 bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 011 23k $0000e $5bff 5k $0000e $13ff 5k $0000e $13ff 1k $5c00e $5fff 16 m program $ffffff $ff0000 $000000 $001400 $fff000 $ffff80 $ffffff $ff0000 $000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-14 dsp56309um/d motorola memory configuration memory maps figure 3-5 16-bit space with default ram (1, 0, 0) aa0558 external internal program ram 20k $ffff $5000 $0000 internal i/o internal x data ram 7k external external i/o internal y data ram 7k external program x data y data bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 100 20k $0000e $4fff 7k $0000e $1bff 7k $0000e $1bff none 64k $ffff $0000 $ff80 $1c00 $ffff $0000 $ff80 $1c00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory maps motorola dsp56309um/d 3-15 figure 3-6 16-bit space with instruction cache enabled (1, 0, 1) aa0562 external internal program ram 19k $ffff $5000 $0000 internal i/o external internal x data ram 7k external i/o external internal y data ram 7k program x data y data i-cache 1k $4c00 $1c00 bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 101 19k $0000e $4bff 7k $0000e $1bff 7k $0000e $1bff 1k $4c00e $4fff 64k $ffff $0000 $ff80 $1c00 $ffff $0000 $ff80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-16 dsp56309um/d motorola memory configuration memory maps figure 3-7 16-bit space with switched program ram (1, 1, 0) aa0560 internal program ram 24k $ffff $0000 internal i/o internal x data ram 5k external external i/o internal y data ram 5k external $ffff $0000 program x data y data $ff80 $1400 $6000 bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 110 24k $0000e $5fff 5k $0000e $13ff 5k $0000e $13ff none 64k external $ffff $0000 $ff80 $1400 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory configuration memory maps motorola dsp56309um/d 3-17 figure 3-8 16-bit space, switched program ram, instruction cache enabled (1, 1, 1) aa0564 external $ffff $0000 internal i/o internal x data ram 5k external $1400 external i/o internal y data ram 5k external program x data y data i-cache 1k $6000 $5c00 bit settings memory configuration sc ms ce program ram x data ram y data ram cache addressable memory size 111 23k $0000e $5fff 5k $0000e $13ff 5k $0000e $13ff 1k $5c00e $5fff 64k internal ram 23k program $ffff $0000 $ff80 $1400 $ffff $0000 $ff80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-18 dsp56309um/d motorola memory configuration internal i/o memory map 3.5 internal i/o memory map the dsp56309 internal x-i/o space (the top 128 locations of the x data memory space) is listed in table d-2 on page d-11 of appendix d?interrupt sources . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 4-1 section 4 core configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-2 dsp56309um/d motorola core configuration 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 bootstrap program . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.4 interrupt sources and priorities . . . . . . . . . . . . . 4-9 4.5 dma request sources . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.6 operating mode register (omr). . . . . . . . . . . . . . . 4-17 4.7 pll control register . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.8 device identification register (idr). . . . . . . . . . . 4-18 4.9 aa control registers (aar0eaar3) . . . . . . . . . . . . 4-19 4.10 jtag boundary scan register (bsr) . . . . . . . . . . . 4-20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration introduction motorola dsp56309um/d 4-3 4.1 introduction this chapter presents details on core configuration specific to the dsp56309. these configuration details include the following: operating modes bootstrap program interrupt sources and priorities dma request sources operating mode register pll control register aa control registers jtag boundary scan register for information on specific registers or modules in the dsp56300 core, refer to the dsp56300 family manual (dsp56300fm/ad) . 4.2 operating modes the dsp56309 begins operation by leaving reset state and going into one of eight operating modes. as the dsp56309 exits the reset state, it loads the values of moda, modb, modc, and modd into bits ma, mb, mc, and md of the operating mode register (omr). these bit settings select the operating mode, which determines the bootstrap program option the microprocessor uses to start up. the maemd bits of the omr can also be set directly by software. a jump directly to the bootstrap program entry point ($ff0000) after the omr bits are set causes the dsp56309 to execute the specified bootstrap program option (except modes 0 and 8). table 4-1 shows the dsp56309 bootstrap operation modes, the corresponding settings of the external operational mode signal lines (the mode bits maemd in the omr), and the reset vector address to which the dsp56309 jumps once it leaves the reset state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-4 dsp56309um/d motorola core configuration bootstrap program 4.3 bootstrap program the bootstrap program is factory-programmed in an internal, 192-word by 24-bit bootstrap rom located in program memory space at locations $ff0000e$ff00bf. the bootstrap program can load any program ram segment from an external byte-wide eprom, the sci, or the host port. the bootstrap program code is listed in appendix a?bootstrap programs . bootstrap operating mode descriptions for the dsp56309 are listed in table 4-1 . table 4-1 dsp56309 operating modes mode modd modc modb moda reset vector description 0 0 0 0 0 $c00000 expanded mode: address $c00000 is reflected as $00000 on port a signals a0-a17 1 0 0 0 1 $ff0000 reserved 2 0 0 1 0 $ff0000 reserved 3 0 0 1 1 $ff0000 reserved 4 0 1 0 0 $ff0000 reserved 5 0 1 0 1 $ff0000 reserved 6 0 1 1 0 $ff0000 reserved 7 0 1 1 1 $ff0000 reserved 8 1 0 0 0 $008000 expanded mode 9 1 0 0 1 $ff0000 boot from byte-wide memory at $d00000 a 1 0 1 0 $ff0000 boot through sci b 1 0 1 1 $ff0000 reserved c 1 1 0 0 $ff0000 hi08 boot in isa mode d 1 1 0 1 $ff0000 hi08 boot in hc11 non-multiplexed mode e 1 1 1 0 $ff0000 hi08 boot in 8051 multiplexed bus mode f 1 1 1 1 $ff0000 hi08 boot in mc68302 mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration bootstrap program motorola dsp56309um/d 4-5 on exiting the reset state, the dsp56309 does the following: 1. samples the moda, modb, modc, and modd signal lines. 2. loads their values into bits ma, mb, mc, and md in the omr. the contents of the ma, mb, mc, and md bits determine which bootstrap mode the dsp56309 enters: 1. if ma, mb, mc, and md are all cleared (bootstrap mode 0), the program bypasses the bootstrap rom, and the dsp56309 starts loading instructions from external program memory location $c00000. 2. if ma, mb, and mc are cleared and md is set (bootstrap mode 8), the program bypasses the bootstrap rom, and the dsp56309 starts loading in instruction values from external program memory location $008000. 3. otherwise (bootstrap modes 1e7), the dsp56309 jumps to the bootstrap program entry point at $ff0000. if the bootstrap program is loading via the host interface (hi08), setting the hf0 bit in the host status register (hsr) causes the dsp56309 to stop loading and begin executing the loaded program at the specified start address. see table 4-1 for a tabular description of the mode bit settings for the operating modes. the bootstrap program options (except modes 0 and 8) can be invoked at any time by setting the ma, mb, mc, and md bits in the omr and jumping to the bootstrap program entry point, $ff0000. software can directly set the mode selection bits in the omr. bootstrap modes 0 and 8 are the normal functioning modes for the dsp56309. bootstrap modes 1e7 are the bootstrap modes proper. bootstrap modes 9, a, c, d, e, f select different, specific devices for loading the bootstrap source. in those bootstrap modes, the bootstrap program expects the following data sequence when downloading the user program through an external port: 1. three bytes defining the number of (24-bit) program words to be loaded 2. three bytes defining the (24-bit) start address to which the user program loads in the dsp56309 program memory 3. the user program (three bytes for each 24-bit program word) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-6 dsp56309um/d motorola core configuration bootstrap program the three bytes for each data sequence must be loaded with the least significant byte first. once the bootstrap program completes loading the specified number of words, it jumps to the specified starting address and executes the loaded program. 4.3.1 mode 0: expanded mode the bootstrap rom is bypassed and the dsp56309 starts fetching instructions beginning at address $c00000. memory accesses are performed using sram memory access type with 31 wait states and no address attributes selected (by default). 4.3.2 modes 1 to 7: reserved these modes are reserved for future use. 4.3.3 mode 8: expanded mode the bootstrap rom is bypassed and the dsp56309 starts fetching instructions beginning at address $008000. memory accesses are performed using sram memory access type with 31 wait states and no address attributes selected. mode modd modc modb moda reset vector description 00000 $c00000 expanded mode mode modd modc modb moda reset vector description 81000 $008000 expanded mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration bootstrap program motorola dsp56309um/d 4-7 4.3.4 mode 9: boot from byte-wide external memory the bootstrap program loads instructions through port a from external byte-wide memory, starting at p:$d00000. the sram memory access type is selected by the values in address attribute register 1 (aar1). thirty-one wait states are inserted between each memory access. address $d00000 is reflected as address $00000 on port a signals ha0-ha17. 4.3.5 mode a: boot from sci instructions are loaded through the sci. the bootstrap program sets the sci to operate in 10-bit asynchronous mode, with one start bit, eight data bits, one stop bit and no parity. data is received in this order; start bit, eight data bits (lsb first), and one stop bit. data is aligned in the sci receive data register with the lsb of the least significant byte of the received data appearing at bit 0. the user must provide an external clock source with a frequency at least 16 times the transmission data rate. each byte received by the sci is echoed back through the sci transmitter to the external transmitter. 4.3.6 mode b: reserved this mode is reserved for future use. mode modd modc modb moda reset vector description 91001 $ff0000 boot from byte-wide memory (at $d00000) mode modd modc modb moda reset vector description a1010 $ff0000 boot through sci mode modd modc modb moda reset vector description b1011 $ff0000 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-8 dsp56309um/d motorola core configuration bootstrap program 4.3.7 modes c, d, e, f: boot from hi08 modes c, d, e, and f enable the programmer to boot through the host interface (hi08) in various ways. 4.3.7.1 mode c: in isa/dsp5630x mode (8-bit bus) in mode c: boot from hi08 in isa/dsp5630x with an 8-bit wide bus, the hi08 is configured to interface with an isa bus or with the memory expansion port of a master dsp5630 n processor. if the host processor sets host flag 0 (hf0) in the hi08 interface control register (hcr) while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.3.7.2 mode d: in hc11 non-multiplexed mode in mode d: boot from hi08 in hc11 non-multiplexed mode, the bootstrap program sets the host interface to interface with the motorola hc11 microcontroller. if the host processor sets host flag 0 (hf0) in the hcr while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. mode modd modc modb moda reset vector description c1100 $ff0000 hi08 bootstrap in isa/dsp5630x mode modd modc modb moda reset vector description d1101 $ff0000 hi08 bootstrap in hc11 non-multiplexed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration interrupt sources and priorities motorola dsp56309um/d 4-9 4.3.7.3 mode e: in 8051 multiplexed bus mode in mode e: boot from hi08 in 8051 multiplexed bus mode, the bootstrap program sets the host interface to interface with the intel 8051 bus. if the host processor sets host flag 0 (hf0) in the hcr while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.3.7.4 mode f: in 68302/68360 bus mode in mode f: boot from hi08 in 68302/68360 bus mode, the bootstrap program sets the host interface to interface with the motorola 68302 or 68360 bus. if the host processor sets host flag 0 (hf0) in the hcr while writing the initialization program, the bootstrap program stops loading instructions, jumps to the starting address specified, and executes the loaded program. 4.4 interrupt sources and priorities dsp56309 interrupt handling, like that of all dsp56300 family members, has been optimized for dsp applications. refer to section 7 of the dsp56300 family manual. the interrupt table is located in the 256 locations of program memory to which the vector base address (vba) register in the program control unit (pcu) points. 4.4.1 interrupt sources each interrupt is allocated two instructions in the table, so there are 128 table entries for interrupt handling. table 4-2 shows the table entry address for each interrupt source. mode modd modc modb moda reset vector description e1110 $ff0000 hi08 bootstrap in 8051 multiplexed bus mode modd modc modb moda reset vector description f1111 $ff0000 hi08 bootstrap in 68302 bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-10 dsp56309um/d motorola core configuration interrupt sources and priorities the dsp56309 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions. in the dsp56309, only 46 of the 128 vector addresses are used for specific interrupt sources. the remaining 82 are reserved. if you know that certain interrupts will not be used, those interrupt vector locations can be used for program or data storage. table 4-2 interrupt sources interrupt starting address interrupt priority level range interrupt source vba:$00 3 hardware reset vba:$02 3 stack error vba:$04 3 illegal instruction vba:$06 3 debug request interrupt vba:$08 3 trap vba:$0a 3 non-maskable interrupt (nmi ) vba:$0c 3 reserved vba:$0e 3 reserved vba:$10 0e2 irqa vba:$12 0e2 irqb vba:$14 0e2 irqc vba:$16 0e2 irqd vba:$18 0e2 dma channel 0 vba:$1a 0e2 dma channel 1 vba:$1c 0e2 dma channel 2 vba:$1e 0e2 dma channel 3 vba:$20 0e2 dma channel 4 vba:$22 0e2 dma channel 5 vba:$24 0e2 timer 0 compare vba:$26 0e2 timer 0 overflow vba:$28 0e2 timer 1 compare vba:$2a 0e2 timer 1 overflow vba:$2c 0e2 timer 2 compare vba:$2e 0e2 timer 2 overflow f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration interrupt sources and priorities motorola dsp56309um/d 4-11 vba:$30 0e2 essi0 receive data vba:$32 0e2 essi0 receive data with exception status vba:$34 0e2 essi0 receive last slot vba:$36 0e2 essi0 transmit data vba:$38 0e2 essi0 transmit data with exception status vba:$3a 0e2 essi0 transmit last slot vba:$3c 0e2 reserved vba:$3e 0e2 reserved vba:$40 0e2 essi1 receive data vba:$42 0e2 essi1 receive data with exception status vba:$44 0e2 essi1 receive last slot vba:$46 0e2 essi1 transmit data vba:$48 0e2 essi1 transmit data with exception status vba:$4a 0e2 essi1 transmit last slot vba:$4c 0e2 reserved vba:$4e 0e2 reserved vba:$50 0e2 sci receive data vba:$52 0e2 sci receive data with exception status vba:$54 0e2 sci transmit data vba:$56 0e2 sci idle line vba:$58 0e2 sci timer vba:$5a 0e2 reserved vba:$5c 0e2 reserved vba:$5e 0e2 reserved vba:$60 0e2 host receive data full vba:$62 0e2 host transmit data empty vba:$64 0e2 host command (default) vba:$66 0e2 reserved ::: vba:$fe 0e2 reserved table 4-2 interrupt sources (continued) interrupt starting address interrupt priority level range interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-12 dsp56309um/d motorola core configuration interrupt sources and priorities 4.4.2 interrupt priority levels the dsp56309 has a four-level interrupt priority structure. each interrupt has two interrupt priority level bits (ipl[1:0]) that determine its interrupt priority level. level 0 is the lowest priority; level 3 is the highest-level priority and is non-maskable. table 4-3 defines the ipl bits. table 4-3 interrupt priority level bits ipl bits interrupts enabled interrupts masked interrupt priority level xxl1 xxl0 00 no ? 0 0 1 yes 0 1 1 0 yes 0, 1 2 1 1 yes 0, 1, 2 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration interrupt sources and priorities motorola dsp56309um/d 4-13 there are two interrupt priority registers in the dsp56309. the iprec is dedicated to dsp56300 core interrupt sources, and iprep is dedicated to dsp56309 peripheral interrupt sources. iprec is shown in figure 4-1 and iprep is shown in figure 4-2 . figure 4-1 interrupt priority register c (ipr-c) (x:$ffffff) figure 4-2 interrupt priority register p (ipr-p) (x:$fffffe) ial0 ial1 ial2 ibl0 ibl1 ibl2 icl0 icl1 icl2 0 1 2 3 4 5 6 7 8 9 10 11 irqa ipl irqa mode irqb ipl irqb mode irqc ipl irqc mode irqd ipl d0l0 d0l1 d1l0 d1l1 23 22 21 20 19 18 17 16 15 14 13 12 dma0 ipl dma1 ipl d2l0 d2l1 d3l0 d3l1 d4l0 d4l1 d5l0 d5l1 dma2 ipl dma3 ipl dma4 ipl dma5 ipl idl2 idl1 idl0 irqd mode hpl0 hpl1 s0l0 s0l1 s1l0 s1l1 23 22 21 20 19 18 17 16 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 hi08 ipl essi0 ipl essi1 ipl sci ipl triple timer ipl t0l0 t0l1 scl0 scl1 reserved reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-14 dsp56309um/d motorola core configuration interrupt sources and priorities 4.4.3 interrupt source priorities within an ipl if more than one interrupt request is pending when an instruction executes, the interrupt source with the highest ipl is serviced first. when several interrupt requests having the same ipl are pending, another fixed-priority structure within that ipl determines which interrupt source is serviced first. this fixed priority list of interrupt sources within an ipl is shown in table 4-4 . table 4-4 interrupt source priorities within an ipl priority interrupt source level 3 (nonmaskable) highest hardware reset ? stack error ? illegal instruction ? debug request interrupt ? trap lowest non-maskable interrupt levels 0, 1, 2 (maskable) highest irqa (external interrupt) ? irqb (external interrupt) ? irqc (external interrupt) ? irqd (external interrupt) ? dma channel 0 interrupt ? dma channel 1 interrupt ? dma channel 2 interrupt ? dma channel 3 interrupt ? dma channel 4 interrupt ? dma channel 5 interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration interrupt sources and priorities motorola dsp56309um/d 4-15 ? host command interrupt ? host transmit data empty ? host receive data full ? essi0 rx data with exception interrupt ? essi0 rx data interrupt ? essi0 receive last slot interrupt ? essi0 tx data with exception interrupt ? essi0 transmit last slot interrupt ? essi0 tx data interrupt ? essi1 rx data with exception interrupt ? essi1 rx data interrupt ? essi1 receive last slot interrupt ? essi1 tx data with exception interrupt ? essi1 transmit last slot interrupt ? essi1 tx data interrupt ? sci receive data with exception interrupt ? sci receive data ? sci transmit data ? sci idle line ? sci timer ? timer0 overflow interrupt ? timer0 compare interrupt ? timer1 overflow interrupt ? timer1 compare interrupt table 4-4 interrupt source priorities within an ipl (continued) priority interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-16 dsp56309um/d motorola core configuration dma request sources 4.5 dma request sources the dma request source bits (drs[4:0]) in the dma control/status registers) encode the source of dma requests used to trigger dma transfers. the dma request sources can be internal peripherals or external devices requesting service through the irqa , irqb , irqc, or irqd signals. table 4-5 describes the meanings of the drs bits. ? timer2 overflow interrupt lowest timer2 compare interrupt table 4-5 dma request sources dma request source bits drs4... drs0 requesting device 00000 external (irqa signal) 00001 external (irqb signal) 00010 external (irqc signal) 00011 external (irqd signal) 00100 transfer done from dma channel 0 00101 transfer done from dma channel 1 00110 transfer done from dma channel 2 00111 transfer done from dma channel 3 01000 transfer done from dma channel 4 01001 transfer done from dma channel 5 01010 essi0 receive data (rdf0 = 1) 01011 essi0 transmit data (tde0 = 1) 01100 essi1 receive data (rdf1 = 1) table 4-4 interrupt source priorities within an ipl (continued) priority interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration operating mode register (omr) motorola dsp56309um/d 4-17 4.6 operating mode register (omr) the omr is a 24-bit, read/write register divided into three byte-sized units. the first two bytes (com and eom) control the chip?s operating mode. the third byte (scs) controls and monitors the stack extension. the omr control bits are shown in figure 4-3 . refer to the dsp56300 family manual for a complete description of the omr. 01101 essi1 transmit data (tde1 = 1) 01110 sci receive data (rdrf = 1) 01111 sci transmit data (tdre = 1) 10000 timer0 (tcf0 = 1) 10001 timer1 (tcf1 = 1) 10010 timer2 (tcf2 = 1) 10011 host receive data full (hrdf = 1) 10100 host transmit data empty (htde = 1) 10101e11111 reserved scs eom com 23222120191817161514131211109876543210 pen sen wrp eov eun xys ate apd abe brt tas be cdp1:0 ms sd ebd md mc mb ma pen?patch enable ate?address tracing enable ms?memory switch mode sen?stack extension enable apd?address priority disable sd?stop delay wrp?extended stack wrap flag abe?asynch. bus arbitration enable ebd?external bus disable eov?extended stack overflow flag brt?bus release timing md?operating mode d eun?extended stack underflow flag tas?ta synchronize select mc?operating mode c xys?stack extension space select be?burst mode enable mb?operating mode b cdp1?core-dma priority 1 ma?operating mode a cdp0?core-dma priority 0 - reserved bit. read as zero, should be written with zero for future compatibility. figure 4-3 dsp56309 operating mode register (omr) table 4-5 dma request sources (continued) dma request source bits drs4... drs0 requesting device f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-18 dsp56309um/d motorola core configuration pll control register 4.7 pll control register the pll control (pctl) register is an x-i/o mapped, 24-bit, read/write register that directs the operation of the on-chip pll. the pctl control bits are shown in figure 4-4 . refer to the dsp56300 family manual for a full description of the pctl. 4.7.1 pctl pll multiplication factor bits 0e11 the multiplication factor bits (mf[11:0]) define the multiplication factor (mf) that is applied to the pll input frequency. the mf bits are cleared during a dsp56309 hardware reset, which corresponds to an mf of one. 4.7.2 pctl xtal disable bit (xtld) bit 16 the xtal disable bit (xtld) controls the on-chip crystal oscillator xtal output. the xtld bit is cleared during a dsp56309 hardware reset, which means that the xtal output signal is active, permitting normal operation of the crystal oscillator. 4.7.3 pctl predivider factor bits (pd0epd3) bits 20e23 the predivider factor bits (pd0epd3) define the predivision factor (pdf) to be applied to the pll input frequency. the pd0epd3 bits are cleared during a dsp56309 hardware reset, which corresponds to a pdf of one. 4.8 device identification register (idr) the device identification register (idr) is a 24-bit, read-only factory programmed register that identifies dsp56300 family members. it specifies the derivative number and 11109876543210 mf11 mf10 mf9 mf8 mf7 mf6 mf5 mf4 mf3 mf2 mf1 mf0 23 22 21 20 19 18 17 16 15 14 13 12 pd3 pd2 pd1 pd0 cod pen pstp xtld xtlr df2 df1 df0 aa0852 figure 4-4 pll control (pctl) register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core configuration aa control registers (aar0eaar3) motorola dsp56309um/d 4-19 revision number of the device. this information can be used in testing or by software. shows the contents of the idr. revision numbers are assigned as follows: $0 is revision 0, $1 is revision a, and so on. because the dsp56309 is based on the dsp56302, its identification number is based on the derivative number and revision number of that device. figure 4-5 identification register configuration (revision 0) 4.9 aa control registers (aar0eaar3) the address attribute register (aar) appears in figure 4-6 . there are four of these registers in the dsp56309 (aar0eaar3), one for each aa signal. for a full description of the address attribute registers see the dsp56300 family manual . address multiplexing is not supported by the dsp56309. bit 6 (bam) of the aars is reserved and should have only 0 written to it. 23 16 15 12 11 0 reserved revision number derivative number $00 $2 $302 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-20 dsp56309um/d motorola core configuration jtag boundary scan register (bsr) 4.10 jtag boundary scan register (bsr) the bsr in the dsp56309 jtag implementation contains bits for all device signal and clock pins and associated control signals. all dsp56309 bidirectional pins have a corresponding register bit in the bsr for pin data and are controlled by an associated control bit in the bsr. the bsr is documented in section 11.5 ? dsp56309 boundary scan register on page 11-13. the jtag code is listed in appendix c?dsp56309 bsdl listing . figure 4-6 address attribute registers (aar0eaar3) (x:$fffff9e$fffff6) bac0 bpen 0 1 byen 2 bat1 3 baap 4 5 6 7 8 9 10 11 bxen 12 13 14 bac8 15 16 17 18 19 20 21 22 23 bat0 bac3 bac2 bac11 bac5 bac7 bac6 bac9 bac10 bac1 bnc3 bnc1 bnc2 bnc0 bac4 bpac - reserved bit external access type aa pin polarity program space enable x data space enable y data space enable reserved packing enable number of address bit to compare address to compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 5-1 section 5 general-purpose i/o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-2 dsp56309um/d motorola general-purpose i/o 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o introduction motorola dsp56309um/d 5-3 5.1 introduction the dsp56309 provides thirty-four bidirectional signals that can be configured as gpio signals or as dedicated peripheral signals. no dedicated gpio signals are provided. all of these signals are gpio by default after reset. the control register settings of the dsp56309?s peripherals determine whether these signals function as gpio or as dedicated peripheral signals. this section describes how signals can function as gpio. 5.2 programming model section 2?signal/connection descriptions of this manual documents the special uses of these signals in detail. there are five groups of these signals. they can be controlled separately or as groups. the groups include the following signals: port b: sixteen gpio signals (shared with the hi08 signals) port c: six gpio signals (shared with the essi0 signals) port d: six gpio signals (shared with the essi1 signals) port e: three gpio signals (shared with the sci signals) timers: three gpio signals (shared with the triple timer signals) 5.2.1 port b signals and registers each of the 16 port b signals not used as a hi08 signal can be configured as a gpio signal. the gpio functionality of port b is controlled by three registers: host control register (hcr), host port gpio data register (hdr), and host port gpio direction register (hddr). these registers are documented in section 6?host interface (hi08) of this manual. 5.2.2 port c signals and registers each of the six port c signals not used as an essi0 signal can be configured as a gpio signal. the gpio functionality of port c is controlled by three registers: port c control register (pcrc), port c direction register (prrc), and port c data register (pdrc). these registers are documented in section 7?enhanced synchronous serial interface (essi) of this manual. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5-4 dsp56309um/d motorola general-purpose i/o programming model 5.2.3 port d signals and registers each of the six port d signals not used as a essi1 signal can be configured as a gpio signal. the gpio functionality of port d is controlled by three registers: port d control register (pcrd), port d direction register (prrd) and port d data register (pdrd). these registers are also documented in section 7?enhanced synchronous serial interface (essi) of this manual. 5.2.4 port e signals and registers each of the three port e signals not used as a sci signal can be configured as a gpio signal. the gpio functionality of port e is controlled by three registers: port e control register (pcre), port e direction register (prre) and port e data register (pdre). these registers are documented in section 8?serial communication interface (sci) of this manual. 5.2.5 triple timer signals each of the three triple timer interface signals (tio0etio2) not used as a timer signal can be configured as a gpio signal. each signal is controlled by the appropriate timer control status register (tcsr0etcsr2). these registers are documented in section 9?triple timer module of this manual. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 6-1 section 6 host interface (hi08) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-2 dsp56309um/d motorola host interface (hi08) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 hi08 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 hi08 host port signals. . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 hi08 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5 hi08 dsp side programmer?s model. . . . . . . . . . . . . 6-8 6.6 hi08-external host programmer?s model . . . . . 6-20 6.7 servicing the host interface . . . . . . . . . . . . . . . . 6-31 6.8 hi08 programming model quick reference. . . . 6-34 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) introduction motorola dsp56309um/d 6-3 6.1 introduction the host interface (hi08) is a byte-wide, full-duplex, double-buffered parallel port that can connect directly to the data bus of a host processor. the hi08 supports a variety of buses and provides glueless connection with a number of industry-standard microcomputers, microprocessors, and dsps. the host bus can operate asynchronously to the dsp core clock, so the hi08 registers are divided into two banks. the host register bank is accessible to the external host and the dsp register bank is accessible to the dsp core. the hi08 supports two classes of interfaces: host processor/microcontroller (mcu) connection interface gpio port signals not used as hi08 port signals can be configured as gpio signals, up to a total of 16. 6.2 hi08 features this section lists the features of the host-to-dsp and dsp-to-host interfaces. further details are given in section 6.5?hi08 dsp side programmer?s model and section 6.8?hi08 programming model quick reference . also, see table 6-13 on page 6-34. 6.2.1 host to dsp core interface mapping: e registers are directly mapped into eight internal x data memory locations data word: e dsp56309 24-bit (native) data words are supported, as are 8-bit and 16-bit words transfer modes: e dsp-to-host e host-to-dsp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-4 dsp56309um/d motorola host interface (hi08) hi08 features e host command handshaking protocols: e software polled e interrupt driven e core dma accesses instructions: e memory-mapped registers allow the standard move instruction to be used to transfer data between the dsp56309 and external hosts. e special movep instruction provides for i/o service capability using fast interrupts. e bit addressing instructions (e.g., bchg, bclr, bset, btst, jclr, jsclr, jset, jsset) simplify i/o service routines. 6.2.2 hi08-to-host processor interface sixteen signals support non-multiplexed or multiplexed buses: e h0eh7/had0ehad7 host data bus (h0eh7) or host multiplexed address/data bus (had0ehad7) e has/ha0 address strobe (has) or host address line (ha0) e ha8/ha1 host address line (ha8) or host address line (ha1) e ha9/ha2 host address line (ha9) or host address line (ha2) e hrw/hrd read/write select (hrw) or read strobe (hrd) e hds/hwr data strobe (hds) or write strobe (hwr) e hcs/ha10 host chip select (hcs) or host address line (ha10 ) e hreq/htrq host request (hreq) or host transmit request (htrq) e hack/hrrq host acknowledge (hack) or host receive request (hrrq) mapping: e hi08 registers are mapped into eight consecutive locations in external bus address space. e the hi08 acts as a memory or i/o-mapped peripheral for microprocessors, microcontrollers, etc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 features motorola dsp56309um/d 6-5 data word: 8-bit transfer modes: e mixed 8-bit, 16-bit, and 24-bit data transfers dsp-to-host host-to-dsp e host command handshaking protocols: e software polled e interrupt-driven (interrupts are compatible with most processors, including the mc68000, 8051, hc11, and hitachi h8.) dedicated interrupts: e separate interrupt lines for each interrupt source e special host commands force dsp core interrupts under host processor control. these commands are useful for these purposes: real-time production diagnostics creating a debugging window for program development host control protocols interface capabilities: e glueless interface (no external logic required) to these devices: motorola hc11 hitachi h8 8051 family thomson p6 family e minimal glue-logic (pullups, pulldowns) required to interface these devices: isa bus motorola 68k family intel x86 family f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-6 dsp56309um/d motorola host interface (hi08) hi08 host port signals 6.3 hi08 host port signals the host port signals are documented in section 2.8?host interface (hi08) . each host port signal can be programmed as a host port signal or as a gpio signal, pb0epb15, as in table 6-1 through table 6-3 . table 6-1 hi08 signal definitions for various operational modes hi08 port signal multiplexed address/data bus mode non-multiplexed bus mode gpio mode had0ehad7 had0ehad7 h0eh7 pb0epb7 has/ha0 has /has ha0 pb8 ha8/ha1 ha8 ha1 pb9 ha9/ha2 ha9 ha2 pb10 hcs/ha10 ha10 hcs /hcs pb13 table 6-2 hi08 data strobe signals hi08 port signal single strobe bus dual strobe bus gpio mode hrw/hrd hrw hrd /hrd pb11 hds/hwr hds /hds hwr /hwr pb12 table 6-3 hi08 host request signals hi08 port signal vector required no vector required gpio mode hreq/ htrq hreq /hreq htrq /htrq pb14 hack/ hrrq hack /hack hrrq /hrrq pb15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 block diagram motorola dsp56309um/d 6-7 6.4 hi08 block diagram figure 6-1 shows the hi08 registers. the top row of registers are for access by the dsp core. the bottom row of registers are for access by the host processor. figure 6-1 hi08 block diagram txl txm txh 8 hpcr latch rxl ivr cvr icr 24 hddr hcr hsr hdr dsp peripheral data bus host bus rxm hbar isr 8 hrx htx core dma data bus rxh h c r = host c ontrol register hsr = host status register hpcr = host port control register hbar = host base address register htx = host transmit register hrx = host receive register hddr = host data direction register hdr = host data register icr = interface control register cvr = command vector register isr = interface status register ivr = interrupt vector register rxh = receive register high rxm = receive register middle rxl = receive register low txh = transmit register high txm = transmit register middle txl = transmit register high address comparator 24 24 24 24 24 24 24 24 24 24 24 8 8 8 8 3 8 8 8 8 8 8 3 5 aa0657 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-8 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5 hi08 dsp side programmer?s model the dsp56309 core treats the hi08 as a memory-mapped peripheral occupying eight 24-bit words in x data memory space. the dsp treats the hi08 as a normal memory-mapped peripheral, employing either standard polled or interrupt-driven programming techniques. separate transmit and receive data registers are double-buffered to allow the dsp and host processor to transfer data efficiently at high speed. direct memory mapping allows the dsp56309 core to communicate with the hi08 registers using standard instructions and addressing modes. in addition, the movep instruction allows direct data transfers between dsp56309 internal memory and the hi08 registers or vice versa . there are two kinds of host processor registers, data and control, with eight registers in all. all eight registers can be accessed by the dsp core but not by the external host. data registers are 24-bit registers used for high-speed data transfer to and from the dsp. host data receive register (hrx) host data transmit register (htx) the dsp side control registers are 16-bit registers that control dsp functions. the eight msbs in the dsp side control registers are read by the dsp56309 as 0. those registers are as follows: host control register (hcr) host status register (hsr) host base address register (hbar) host port control register (hpcr) host gpio data direction register (hddr) host gpio data register (hdr) both hardware reset signals and software reset instructions disable the hi08. after reset, the hi08 signals are configured to gpio and disconnected from the dsp56309 core (i.e., the signals are left floating). 6.5.1 host receive data register (hrx) the hrx register handles host-to-dsp data transfers. the dsp56309 views it as a 24-bit read-only register. its address is x:$ffffc6. it is loaded with 24-bit data from the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-9 transmit data registers (txh:txm:txl on the host side) when both the host?s transmit data register empty (isr:txde) bit and the dsp?s host receive data full (hsr:hrdf) bits are cleared. the transfer operation sets both the txde and hrdf bits. when the hrdf bit is set, the hrx register contains valid data. the dsp56309 sets the hrie bit (hcr, bit 0) to cause a host receive data interrupt when hrdf is set. when the dsp56309 reads the hrx register, the hrdf bit is cleared. 6.5.2 host transmit data register (htx) the htx register handles for dsp-to-host data transfers. the dsp56309 views it as a 24-bit write-only register. its address is x:$ffffc7. writing to the htx register clears the dsp?s host transfer data empty (hsr:htde) bit. the contents of the htx register are transferred as 24-bit data to the receive byte registers (rxh:rxm:rxl) when both the htde and the host?s receive data full (isr:rxdf) bits are cleared. this transfer operation sets the htde and rxdf bits. the dsp56309 sets the htie bit to cause a host transmit data interrupt when htde is set. to prevent the previous data from being overwritten, data should not be written to the htx until the htde bit is set. note: during data writes to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by this operation are updated. if you read any of those status bits within the next two cycles, the bit does not reflect its current status. see the dsp56300 family manual, appendix b, polling a peripheral device for write for further details. 6.5.3 host control register (hcr) the hcr is a 16-bit, read/write control register by which the dsp core controls the hi08 operating mode. initialization values for hcr bits are documented in section 6.5.9?dsp side registers after reset . reserved bits are read as 0 and should be written with 0 for future compatibility. 1514131211109876543210 hf3 hf2 hcie htie hrie ?reserved bit, read as 0, should be written with 0 for future compatibility. aa0658 figure 6-2 host control register (hcr) (x:$ffffc2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-10 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5.3.1 hcr host receive interrupt enable (hrie) bit 0 the hrie bit generates a host receive data interrupt request if the host receive data full (hrdf) bit in the host status register (hsr, bit 0), is set. the hrdf bit is set when data is written to the hrx. if hrie is cleared, hrdf interrupts are disabled. 6.5.3.2 hcr host transmit interrupt enable (htie) bit 1 the htie bit generates a host transmit data interrupt request if the host transmit data empty (htde) bit in the hsr is set. the htde bit is set when data is read from the htx. if htie is cleared, htde interrupts are disabled. 6.5.3.3 hcr host command interrupt enable (hcie) bit 2 the hcie bit generates a host command interrupt request if the host command pending (hcp) status bit in the hsr is set. if hcie is cleared, hcp interrupts are disabled. the interrupt address is determined by the host command vector register (cvr). note: if more than one interrupt request source is asserted and enabled (e.g., hrdf is set, hcp is set, hrie is set, and hcie is set), the hi08 generates interrupt requests according to priorities shown in table 6-4 . 6.5.3.4 hcr host flags 2,3 (hf[3:2]) bits 3, 4 hf[3:2] bits are general-purpose flags for dsp-to-host communication. the dsp core sets and clears them. the values of hf[3:2] are reflected in the interface status register (isr); that is, if they are modified by the dsp software, the host processor can read the modified values by reading the isr. these two flags can be used individually or as encoded pairs in a simple dsp-to-host communication protocol, implemented in both the dsp and the host processor software. 6.5.3.5 hcr reserved bits 5-15 these bits are reserved. they are read as 0 and should be written with 0. table 6-4 host command interrupt priority list priority interrupt source highest host command (hcp = 1) transmit data (htde = 1) lowest receive data (hrdf = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-11 6.5.4 host status register (hsr) the hsr is a 16-bit, read-only status register by which the dsp reads the hi08 status and flags. the host processor cannot access it directly. reserved bits are read as 0 and should be written with 0. the initialization values for the hsr bits are described in section 6.5.9?dsp side registers after reset on page 6-18. 6.5.4.1 hsr host receive data full (hrdf) bit 0 the hrdf bit indicates that the host receive data register (hrx) contains data from the host processor. hrdf is set when data is transferred from the txh:txm:txl registers to the hrx register. if hrdf is set, the hi08 generates a receive data full dma request. hrdf is cleared when the dsp core reads the hrx. hrdf is also cleared when the host processor uses the initialize function. 6.5.4.2 hsr host transmit data empty (htde) bit 1 the htde bit indicates that the host transmit data register (htx) is empty and can be written by the dsp core. htde is set when the htx register is transferred to the rxh:rxm:rxl registers. htde is also set when the host processor uses the initialize function. if htde is set, the hi08 generates a transmit data full dma request. htde is cleared when htx is written by the dsp core. 6.5.4.3 hsr host command pending (hcp) bit 2 the hcp bit indicates that the host has set the hc bit and that a host command interrupt is pending. the hcp bit reflects the status of the hc bit in the cvr. hc and hcp are cleared by the hi08 hardware when the interrupt request is serviced by the dsp core. if the host clears hc, hcp is also cleared. 6.5.4.4 hsr host flags 0, 1 (hf[1:0]) bits 3, 4 hf[1:0] bits are used as general-purpose flags for host-to-dsp communication. hf[1:0] can be set or cleared by the host. these bits reflect the status of host flags hf[1:0] in the icr on the host side. they can be used individually or as encoded pairs in a simple host-to-dsp communication protocol implemented in both the dsp and the host processor software. 6.5.4.5 hsr reserved bits 5-15 these bits are reserved. they are read as 0 and should be written with 0. 1514131211109876543210 hf1 hf0 hcp htde hrdf ?reserved bit, read as 0, should be written with 0 for future compatibility. aa0659 figure 6-3 host status register (hsr) (x:$ffffc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-12 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5.5 host base address register (hbar) the hbar is used in multiplexed bus modes. this register, illustrated in figure 6-4 , selects the base address where the host side registers are mapped into the bus address space. the address from the host bus is compared with the base address as programmed in the base address register. if the addresses match, an internal chip select is generated. the use of this register by the chip select logic is described in figure 6-5 . 6.5.5.1 hbar base address (ba[10:3]) bits 0-7 these bits reflect the base address where the host-side registers are mapped into the bus address space. 6.5.5.2 hbar reserved bits 8-15 these bits are reserved. they are read as 0 and should be written with 0. 6.5.6 host port control register (hpcr) the hpcr is a 16-bit, read/write control register by which the dsp controls the hi08 operating mode. reserved bits are read as 0 and should be written with 0 for future compatibility. the initialization values for the hpcr bits are described in section 6.5.9?dsp side registers after reset . the hpcr bits are illustrated in figure 6-6 . 1514131211109876543210 ba10 ba9 ba8 ba7 ba6 ba5 ba4 ba3 aa0665 figure 6-4 host base address register (hbar) (x:$ffffc5) figure 6-5 self chip select logic had[0e7] chip select comparator a[3:7] 8 bits has ha[8:10] dsp peripheral data bus aa0666 latch base address register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-13 note: to assure proper operation of the dsp56309, the hpcr bits hap, hrp, hcsp, hdds, hmux, hasp, hdsp, hrod, haen, and hren should be changed only if hen is cleared. to assure proper operation of the dsp56309, the hpcr bits hap, hrp, hcsp, hdds, hmux, hasp, hdsp, hrod, haen, hren, hcsen, ha9en, and ha8en should not be set when hen is set or simultaneously with setting hen. 6.5.6.1 hpcr host gpio port enable (hgen) bit 0 if hgen is set, signals configured as gpio are enabled. if this bit is cleared, signals configured as gpio are disconnected; outputs are high impedance, and inputs are electrically disconnected. signals configured as hi08 are not affected by the value of hgen. 6.5.6.2 hpcr host address line 8 enable (ha8en) bit 1 if ha8en is set and the hi08 is in multiplexed bus mode, then ha8/a1 acts as host address line 8 (ha8). if this bit is cleared and the hi08 is in multiplexed bus mode, then ha8/ha1 acts as a gpio signal according to the value of the hddr and hdr. note: ha8en is ignored when the hi08 is not in the multiplexed bus mode (hmux is cleared). 6.5.6.3 hpcr host address line 9 enable (ha9en) bit 2 if ha9en is set and the hi08 is in multiplexed bus mode, then ha9/ha2 acts as host address line 9 (ha9). if this bit is cleared, and the hi08 is in multiplexed bus mode, then ha9/ha2 is configured as a gpio signal according to the value of the hddr and hdr. note: ha9en is ignored when the hi08 is not in the multiplexed bus mode (hmux is cleared). 6.5.6.4 hpcr host chip select enable (hcsen) bit 3 if the hcsen bit is set, then hcs/ha10 is used as host chip select (hcs) in the non-multiplexed bus mode (hmux is cleared), and as host address line 10 (ha10) in the multiplexed bus mode (hmux is set). if this bit is cleared, then hcs/ha10 is configured as a gpio signal according to the value of the hddr and hdr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 hap hrp hcsp hdds hmux hasp hdsp hrod hen haen hren hcsen ha9en ha8en hgen ?reserved bit, read as 0, should be written with 0 for future compatibility. aa0660 figure 6-6 host port control register (hpcr) (x:$ffffc4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-14 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5.6.5 hpcr host request enable (hren) bit 4 the hren bit controls the host request signals. if hren is set and the hi08 is in the single host request mode (hdrq is cleared in the host interface control register (icr)), hreq/htrq is configured as the host request (hreq) output. if hren is cleared, hreq/htrq and hack/hrrq are configured as gpio signals according to the value of the hddr and hdr. if hren is set in the double host request mode (hdrq is set in the icr), hreq/htrq is configured as the host transmit request (htrq) output and hack/hrrq as the host receive request (hrrq) output. if hren is cleared, hreq/htrq and hack/hrrq are configured as gpio signals according to the value of the hddr and hdr. 6.5.6.6 hpcr host acknowledge enable (haen) bit 5 the haen bit controls the hack signal. in the single host request mode (hdrq is cleared in the icr), if haen and hren are both set, hack/hrrq is configured as the host acknowledge (hack) input. if haen or hren is cleared, hack/hrrq is configured as a gpio signal according to the value of the hddr and hdr. in the double host request mode (hdrq is set in the icr), haen is ignored. 6.5.6.7 hpcr host enable (hen) bit 6 if hen is set, the hi08 operates as the host interface. if hen is cleared, the hi08 is not active, and all the hi08 signals are configured as gpio signals according to the value of the hddr and hdr. 6.5.6.8 hpcr reserved bit 7 this bit is reserved. it is read as 0 and should be written as 0. 6.5.6.9 hpcr host request open drain (hrod) bit 8 the hrod bit controls the output drive of the host request signals. in the single host request mode (hdrq is cleared in icr), if hrod is cleared and host requests are enabled (hren is set and hen is set in hpcr), the hreq signal is always driven by the hi08. if hrod is set and host requests are enabled, the hreq signal is an open drain output. in the double host request mode (hdrq is set in the icr), if hrod is cleared and host requests are enabled (hren is set and hen is set in the hpcr), the htrq and hrrq signals are always driven. if hrod is set and host requests are enabled, the htrq and hrrq signals are open drain outputs. 6.5.6.10 hpcr host data strobe polarity (hdsp) bit 9 if hdsp is cleared, the data strobe signals are configured as active low inputs, and data is transferred when the data strobe is low. if hdsp is set, the data strobe signals are configured as active high inputs, and data is transferred when the data strobe is high. the data strobe signals are either hds by itself or both hrd and hwr together. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-15 6.5.6.11 hpcr host address strobe polarity (hasp) bit 10 if hasp is cleared, the host address strobe (has) signal is an active low input, and the address on the host address/data bus is sampled when the has signal is low. if hasp is set, has is an active high address strobe input, and the address on the host address or data bus is sampled when the has signal is high. 6.5.6.12 hpcr host multiplexed bus (hmux) bit 11 if hmux is set, the hi08 latches the lower portion of a multiplexed address/data bus. in this mode the internal address line values of the host registers are taken from the internal latch. if hmux is cleared, it indicates that the hi08 is connected to a non-multiplexed type of bus. the values of the address lines are then taken from the hi08 input signals. 6.5.6.13 hpcr host dual data strobe (hdds) bit 12 if the hdds bit is cleared, the hi08 operates in the single-strobe bus mode. in this mode, the bus has a single data strobe signal for both reads and writes. if set, the hi08 operates in the dual-strobe bus mode. in this mode, the bus has two separate data strobes, one for data reads, the other for data writes. see figure 6-7 and figure 6-8 for more information on the two types of buses. . figure 6-7 single strobe bus hrw hds in a single-strobe bus, a ds (data strobe) signal qualifies the access, while a r/w (read-write) signal specifies the direction of the access. aa0661 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-16 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5.6.14 hpcr host chip select polarity (hcsp) bit 13 if the hcsp bit is cleared, the host chip select (hcs) signal is configured as an active low input and the hi08 is selected when the hcs signal is low. if the hcsp signal is set, hcs is configured as an active high input, and the hi08 is selected when the hcs signal is high. 6.5.6.15 hpcr host request polarity (hrp) bit 14 the hrp bit controls the polarity of the host request signals. in the single-host request mode (hdrq is cleared in the icr), if hrp is cleared, and host requests are enabled (hren is set and hen is set), the hreq signal is an active low output. if hrp is set and host requests are enabled, the hreq signal is an active high output. in the double-host request mode (hdrq is set in the icr), if hrp is cleared, and host requests are enabled (hren is set and hen is set), the htrq and hrrq signals are active low outputs. if hrp is set, and host requests are enabled, the htrq and hrrq signals are active high outputs. 6.5.6.16 hpcr host acknowledge polarity (hap) bit 15 if the hap bit is cleared, the host acknowledge (hack) signal is configured as an active low input. the hi08 drives the contents of the ivr onto the host bus when the hack signal is low. if the hap bit is set, the hack signal is configured as an active high input. the hi08 outputs the contents of the ivr when the hack signal is high. figure 6-8 dual strobe bus data hwr data hrd in dual strobe bus, there are separate hrd and hwr signals that specify the access as being a read or write access, respectively. read data out read cycle write cycle write data in aa0662 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-17 6.5.7 host data direction register (hddr) the hddr controls the direction of the data flow for each of the hi08 signals configured as gpio. it is illustrated in figure 6-9 . even when the hi08 functions as the host interface, its unused signals can be configured as gpio signals. for information on the hi08 gpio configuration options, see section 6.6.8?general-purpose i/o on page 6-30. if bit drxx is set, the corresponding hi08 signal is configured as an output signal. if bit drxx is cleared, the corresponding hi08 signal is configured as an input signal. 6.5.8 host data register (hdr) the hdr register holds the data value of the corresponding bits of the hi08 signals configured as gpio signals. it is illustrated in figure 6-10 . the functionality of the dxx bit depends on the corresponding hddr bit (drxx), as in table 6-5 . the hdr cannot be accessed by the host processor. 1514131211109876543210 dr15 dr14 dr13 dr12 dr11 dr10 dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 aa0663 figure 6-9 host data direction register (hddr) (x:$ffffc8) 1514131211109876543210 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 aa0664 figure 6-10 host data register (hdr) (x:$ffffc9) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-18 dsp56309um/d motorola host interface (hi08) hi08 dsp side programmer?s model 6.5.9 dsp side registers after reset table 6-6 shows the results of the four reset types on the bits in each of the hi08 registers accessible by the dsp56309. reset types are as follows: hardware reset (hw) ? caused by the reset signal software reset (sw) ? caused by executing the reset instruction individual reset (ir) ? caused by clearing the hpcr:hen stop reset (st) ? caused by executing the stop instruction. table 6-5 hdr and hddr functionality hddr hdr drxx dxx configured as gpio signal configured as non-gpio signal 0 read only bit? the value read is the binary value of the signal. the corresponding signal is configured as an input. read only bit?does not contain significant data. 1 read/write bit? the value written is the value read. the corresponding signal is configured as an output, and is driven with the data written to dxx. read/write bit? the value written is the value read. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 dsp side programmer?s model motorola dsp56309um/d 6-19 6.5.10 host interface dsp core interrupts the hi08 can request interrupt service from either the dsp56309 or the host processor. the dsp56309 interrupts are internal and do not require the use of an external interrupt signal. when the appropriate interrupt enable bit in the hcr is set, an interrupt condition caused by the host processor sets the appropriate bit in the hsr, generating an interrupt request to the dsp56309. (see figure 6-11 .) the dsp56309 acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. there are three possible interrupts: host command transmit data register empty receive data register full although there is a set of vectors reserved for host command use, the host command can access any interrupt vector in the interrupt vector table. the dsp interrupt service table 6-6 dsp side registers after reset register name register data reset type hw reset sw reset ir reset st reset hcr all bits 0 0 bit value indeterminate after reset ? hpcr all bits 0 0 ? ? hsr hf[1:0] 0 0 ? ? hcp 0 0 0 0 htde 1 1 1 1 hrdf 0 0 0 0 hbar ba[10:3] $80 $80 ? ? hddr dr[15:0] 0 0 ? ? hdr d[15:0] ? ? ? ? hrx hrx [23:0] empty empty empty empty htx htx [23:0] empty empty empty empty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-20 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model routine must read or write the appropriate hi08 register (e.g., clearing hrdf or htde) to clear the interrupt. for host command interrupts, the interrupt acknowledge from the dsp56309 program controller clears the pending interrupt condition. 6.6 hi08-external host programmer?s model the hi08 is a simple, high speed interface to a host processor. to the host bus, the hi08 appears to be eight byte-wide registers. separate transmit and receive data registers are double-buffered to allow the dsp core and host processor to transfer data efficiently at high speed. the host can access the hi08 asynchronously by using polling techniques or interrupt-based techniques. the hi08 appears to the host processor as a memory-mapped peripheral occupying eight bytes in the host processor address space, as in table 6-7 on page 6-22. the eight hi08 registers include the following: a control register (icr) a status register (isr) three data registers (rxh/txh, rxm/txm, and rxl/txl) two vector registers (ivr and cvr) figure 6-11 hsr-hcr operation aa0667 15 x:hcr x:hsr 0 enable hf3 hf2 hcie htie hrie hcr hf1 hf0 hcp htde hrdf hsr status dsp core interrupts receive data full transmit data empty host command 15 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08-external host programmer?s model motorola dsp56309um/d 6-21 the cvr is a special command register by which the host processor issues commands to the dsp56309. only the host processor can access this register. host processors can use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the hi08 registers. the hi08 registers are aligned so that 8-bit host processors can use 8/16/24-bit load and store instructions for data transfers. the hreq/htrq and hack/hrrq handshake flags are provided for polled or interrupt-driven data transfers with the host processor. because of the speed of the dsp56309 interrupt response, most host microprocessors can load or store data at their maximum programmed i/o instruction rate without testing the handshake flags for each transfer. if full handshake is not needed, the host processor can treat the dsp56309 as a fast device, and data can be transferred between the host processor and the dsp56309 at the fastest host processor data rate. one of the most innovative features of the host interface is the host command feature. with this feature, the host processor can issue vectored interrupt requests to the dsp56309. the host can select any of 128 dsp interrupt routines for execution by writing a vector address register in the hi08. this flexibility allows the host processor to execute up to 128 pre-programmed functions inside the dsp56309. for example, use of the dsp56309 host interrupts can allow the host processor to read or write dsp registers (x, y, or program memory locations), force interrupt handlers (e.g., ssi, sci, irqa , irqb interrupt routines), and perform control and debugging operations. note: when the dsp enters stop mode, the hi08 signals are electrically disconnected internally, thus disabling the hi08 until the core leaves stop mode. while the hi08 configuration remains unchanged in stop mode, the core cannot be restarted via the hi08 interface. do not issue a stop command to the dsp via the hi08 unless some other mechanism for exiting stop mode is provided. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-22 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model 6.6.1 interface control register (icr) the icr is an 8-bit, read/write control register by which the host processor controls the hi08 interrupts and flags. it is illustrated in figure 6-12 . the dsp core cannot access the icr. the icr is a read/write register, which allows the use of bit manipulation instructions on control register bits. the control bits are described in the following paragraphs. table 6-7 host side register map host address big endian hlend = 0 little endian hlend = 1 0 icr icr interface control 1 cvr cvr command vector 2 isr isr interface status 3 ivr ivr interrupt vector 4 00000000 00000000 unused 5 rxh/txh rxl/txl receive/transmit bytes 6 rxm/txm rxm/txm 7 rxl/txl rxh/txh host data bus h0 - h7 host data bus h0 - h7 76543210 init hlend hf1 hf0 hdrq treq rreq ?reserved bit. read as 0. should be written with 0, for future compatibility. aa0668 figure 6-12 interface control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08-external host programmer?s model motorola dsp56309um/d 6-23 6.6.1.1 icr receive request enable (rreq) bit 0 the rreq bit controls the hreq signal for host receive data transfers. rreq enables host requests via the host request (hreq or hrrq) signal when the receive data register full (rxdf) status bit in the isr is set. if rreq is cleared, rxdf interrupts are disabled. if rreq and rxdf are set, the host request signal (hreq or hrrq) is asserted. 6.6.1.2 icr transmit request enable (treq) bit 1 treq enables host requests via the host request (hreq or htrq) signal when the transmit data register empty (txde) status bit in the isr is set. if treq is cleared, txde interrupts are disabled. if treq and txde are set, the host request signal is asserted. table 6-8 and table 6-9 summarize the effect of rreq and treq on the hreq and hrrq signals. 6.6.1.3 icr double host request (hdrq) bit 2 if cleared, the hdrq bit configures hreq/htrq and hack/hrrq as hreq and hack, respectively. if hdrq is set, hreq/htrq and hack/hrrq are configured as htrq and hrrq, respectively. table 6-8 treq and rreq modes (hdrq = 0) treq rreq hreq signal 0 0 no interrupts (polling) 0 1 rxdf request (interrupt) 1 0 txde request (interrupt) 1 1 rxdf and txde request (interrupts) table 6-9 treq and rreq modes (hdrq = 1) treq rreq htrq single hrrq signal 0 0 no interrupts (polling) no interrupts (polling) 0 1 no interrupts (polling) rxdf request (interrupt) 1 0 txde request (interrupt) no interrupts (polling) 1 1 txde request (interrupt) rxdf request (interrupt) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-24 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model 6.6.1.4 icr host flag 0 (hf0) bit 3 the hf0 bit is a general-purpose flag for host-to-dsp communication. the host processor can set or clear hf0, and the dsp56309 cannot change this bit. hf0 is reflected in the hsr on the dsp side of the hi08. 6.6.1.5 icr host flag 1 (hf1) bit 4 the hf1 bit is a general-purpose flag for host-to-dsp communication. the host processor can set or clear hf1, and the dsp56309 cannot change this bit. hf1 is reflected in the hsr on the dsp side of the hi08. 6.6.1.6 icr host little endian (hlend) bit 5 if the hlend bit is cleared, the host can access the hi08 in big endian byte order. if set, the host can access the hi08 in little endian byte order. if the hlend bit is cleared the rxh/txh register is located at address $5, the rxm/txm register at $6, and the rxl/txl register at $7. if the hlend bit is set, the rxh/txh register is located at address $7, the rxm/txm register at $6, and the rxl/txl register at $5. 6.6.1.7 icr reserved bit 6 this bit is reserved. it is read as 0 and should be written with 0. 6.6.1.8 icr initialize bit (init) bit 7 the host processor uses the init bit to force initialization of the hi08 hardware. during initialization, the hi08 transmit and receive control bits are configured. using the init bit to initialize the hi08 hardware may or may not be necessary, depending on the software design of the interface. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08-external host programmer?s model motorola dsp56309um/d 6-25 the t ype of initialization done when the init bit is set depends on the state of treq and rreq in the hi08. the init command, which is local to the hi08, can conveniently configure the hi08 into the desired data transfer mode. the effect of the init command is described in table 6-10 . when the host sets the init bit, the hi08 hardware executes the init command. the interface hardware clears the init bit after the command has been executed. 6.6.2 command vector register (cvr) the host processor uses the cvr to cause the dsp56309 to execute an interrupt. the host command feature is independent of any of the data transfer mechanisms in the hi08. it can cause any of the 128 possible interrupt routines in the dsp core to be executed. this register is illustrated in figure 6-13 . 6.6.2.1 cvr host vector (hv[6:0]) bits 0e6 the seven hv bits select the host command interrupt address to be used by the host command interrupt logic. when the host command interrupt is recognized by the dsp interrupt control logic, the address of the interrupt routine taken is 2 hv. the host can write hc and hv in the same write cycle. the host processor can select any of the 128 possible interrupt routine starting addresses in the dsp by writing the interrupt routine address divided by two into the hv bits. this means that the host processor can force any of the existing interrupt handlers (ssi, sci, table 6-10 init command effects treq rreq after init execution transfer direction initialized 0 0 init = 0 none 0 1 init = 0; rxdf = 0; htde = 1 dsp to host 1 0 init = 0; txde = 1; hrdf = 0 host to dsp 1 1 init = 0; rxdf = 0; htde = 1; txde = 1; hrdf = 0 host to/from dsp 76543210 hc hv6 hv5 hv4 hv3 hv2 hv1 hv0 aa0669 figure 6-13 command vector register (cvr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-26 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model irqa, irqb, etc.) and can use any of the reserved or otherwise unused addresses (provided they have been pre-programmed in the dsp). hv is set to $32 (vector location $0064) by a hardware reset signal, software reset instruction, individual reset, or a stop instruction. 6.6.2.2 cvr host command bit (hc) bit 7 the host processor uses the hc bit to handshake the execution of host command interrupts. normally, the host processor sets hc to request a host command interrupt from the dsp56309. when the dsp56309 acknowledges the host command interrupt, the hi08 hardware clears the hc bit. the host processor can read the state of hc to determine when the host command has been accepted. after setting hc, the host must not write to the cvr again until the hi08 hardware clears hc. setting the hc bit causes host command pending (hcp) to be set in the hsr. the host can write to the hc and hv bits in the same write cycle. 6.6.3 interface status register (isr) the interface status register (isr) is an 8-bit, read-only status register used by the host processor to interrogate the status and flags of the hi08. the host processor can write to this address without affecting the internal state of the hi08. the dsp core cannot access the isr. the isr bits are described in the following paragraphs. this register is illustrated in figure 6-14 . 6.6.3.1 isr receive data register full (rxdf) bit 0 the rxdf bit indicates that the receive byte registers (rxh:rxm:rxl) contain data from the dsp56309 and can be read by the host processor. rxdf is set when the htx is transferred to the receive byte registers. rxdf is cleared when the receive data (rxl or rxh according to hlend bit) register is read by the host processor. rxdf can be cleared by the host processor using the initialize function. rxdf can assert the external hreq signal if the rreq bit is set. regardless of whether the rxdf interrupt is enabled, rxdf indicates whether the rx registers are full and data can be latched out so that the host processor can use polling techniques. 76543210 hreq hf3 hf2 trdy txde rxdf ?reserved bit. read as 0. should be written with 0, for future compatibility. aa0670 figure 6-14 interface status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08-external host programmer?s model motorola dsp56309um/d 6-27 6.6.3.2 isr transmit data register empty (txde) bit 1 the txde bit indicates that the transmit byte registers (txh:txm:txl) are empty and can be written by the host processor. txde is set when the contents of the transmit byte registers are transferred to the hrx register. txde is cleared when the transmit (txl or txh according to hlend bit) register is written by the host processor. the host processor can set txde using the initialize function. txde can assert the external htrq signal if the treq bit is set. regardless of whether the txde interrupt is enabled, txde indicates whether the tx registers are full and data can be latched in so that the host processor can use polling techniques. 6.6.3.3 isr transmitter ready (trdy) bit 2 the trdy status bit indicates that txh:txm:txl, and the hrx registers are empty. trdy = txde and hrdf if trdy is set, the data that the host processor writes to txh:txm:txl is immediately transferred to the dsp side of the hi08. this feature has many applications. for example, if the host processor issues a host command which causes the dsp56309 to read the hrx, the host processor can be guaranteed that the data it just transferred to the hi08 is that being received by the dsp56309. 6.6.3.4 isr host flag 2 (hf2) bit 3 hf2 indicates the state of host flag 2 in the hcr on the dsp side. hf2 can be changed only by the dsp56309, as documented in section 6.5.3.4?hcr host flags 2,3 (hf[3:2]) bits 3, 4 on page 6-10. 6.6.3.5 isr host flag 3 (hf3) bit 4 hf3 indicates the state of host flag 3 in the hcr on the dsp side. hf3 can be changed only by the dsp56309, as documented in section 6.5.3.4?hcr host flags 2,3 (hf[3:2]) bits 3, 4 on page 6-10. 6.6.3.6 isr reserved bits 5, 6 these bits are reserved. they are read as 0 and should be written with 0. 6.6.3.7 isr host request (hreq) bit 7 hreq indicates the status of the external transmit and receive request output signals (htrq and hrrq) if hdrq is set. if hdrq is cleared, it indicates the status of the external host request output signal (hreq). table 6-11 shows possible settings of hrdq and hdeq and their effects. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-28 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model table 6-11 hreq and hdrq settings the hreq is set from either or both of two conditions?either the receive byte registers are full or the transmit byte registers are empty. these conditions are indicated by the isr rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associated request enable bit in the icr, hreq is set if one or more of the two enabled interrupt sources is set. 6.6.4 interrupt vector register (ivr) the ivr is an 8-bit, read/write register which typically contains the interrupt vector number used with mc68000 family processor vectored interrupts. only the host processor can read and write this register. the contents of the ivr are placed on the host data bus, h[7:0], when both the hreq and hack signals are asserted. the contents of this register are initialized to $0f by a hardware reset signal or software reset instruction. this value corresponds to the uninitialized interrupt vector in the mc68000 family. this register is illustrated in figure 6-15 . 6.6.5 receive byte registers (rxh: rxm: rxl) the receive byte registers are viewed by the host processor as three 8-bit, read-only registers. these registers are the receive high register (rxh), the receive middle register (rxm), and the receive low register (rxl). they receive data from the high, middle, and hdrq hreq effect 0 0 hreq is cleared; no host processor interrupts are requested. 0 1 hreq is set; an interrupt is requested. 1 0 htrq and hrrq are cleared, no host processor interrupts are requested. 1 1 htrq or hrrq are set; an interrupt is requested. 76543210 iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 aa0671 figure 6-15 interrupt vector register (ivr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08-external host programmer?s model motorola dsp56309um/d 6-29 low bytes, respectively, of the htx register and are selected by the external host address inputs (ha[2:0]) during a host processor read operation. the memory address of the receive byte registers is set by the hlend bit in the icr. if the hlend bit is set, the rxh is located at address $7, rxm at $6, and rxl at $5. if the hlend bit is cleared, the rxh is located at address $5, rxm at $6, and rxl at $7. when data is written to the receive byte register at host address $7, the receive data register full (rxdf) bit is set. the host processor can program the rreq bit to assert the external hreq signal when rxdf is set. this indicates that the hi08 has a full word (either 8, 16, or 24 bits) for the host processor. the host processor can program the rreq bit to assert the external hreq signal when rxdf is set. asserting the hreq signal informs the host processor that the receive byte registers have data to be read. when the host reads the receive byte register at host address $7, the rxdf bit is cleared. 6.6.6 transmit byte registers (txh:txm:txl) the host processor views the transmit byte registers as three 8-bit, write-only registers. these registers are the transmit high register (txh), the transmit middle register (txm), and the transmit low register (txl). these registers send data to the high, middle, and low bytes, respectively, of the hrx register and are selected by the external host address inputs, ha[2:0], during a host processor write operation. if the hlend bit in the icr is set, the txh register is located at address $7, the txm register at $6 and the txl register at $5. if the hlend bit in the icr is cleared, the txh register is located at address $5, the txm register at $6, and the txl register at $7. data is written into the transmit byte registers when the transmit data register empty (txde) bit is set. the host processor programs the treq bit to assert the external hreq/htrq signal when txde is set. this informs the host processor that the transmit byte registers are empty. writing to the data register at host address $7 clears the txde bit. the contents of the transmit byte registers are transferred as 24-bit data to the hrx register when both the txde and the hrdf bit are cleared. this transfer operation sets txde and hrdf. note: when data is written to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by this operation are updated. if you read any of those status bits within the next two cycles, the bit does not reflect its current status. see the dsp56300 family manual, appendix b, polling a peripheral device for write for further details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-30 dsp56309um/d motorola host interface (hi08) hi08-external host programmer?s model 6.6.7 host side registers after reset table 6-12 shows the result of the four kinds of reset on bits in each of the hi08 registers seen by the host processor. the hardware reset is caused by asserting the reset signal. the software reset is caused by executing the reset instruction. the individual reset is caused by clearing the hen bit in the hpcr. the stop reset is caused by executing the stop instruction. 6.6.8 general-purpose i/o when configured as gpio, the hi08 is viewed by the dsp56309 as memory-mapped registers, as documented in section 6.5?hi08 dsp side programmer?s model on page 6-8. those memory-mapped registers control up to 16 i/o signals. software reset instructions and hardware reset signals clear all dsp side control registers and configure the hi08 as gpio with all 16 signals disconnected. external circuitry table 6-12 host side registers after reset register name register data reset type hw reset sw reset ir reset st reset icr all bits 0 0 ? ? cvr hc 0 0 0 0 hv[0:6] $32 $32 ? ? isr hreq 0 0 1 if treq is set; 0 otherwise 1 if treq is set; 0 otherwise hf3 -hf2 0 0 ? ? trdy 1 1 1 1 txde 1 1 1 1 rxdf 0 0 0 0 ivr iv[0:7] $0f $0f ? ? rx rxh: rxm:rxl empty empty empty empty tx txh: txm:txl empty empty empty empty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) servicing the host interface motorola dsp56309um/d 6-31 connected to the hi08 may need external pull-up/pull-down resistors until the signals are configured for operation. the registers cleared are the hpcr, hddr, and hdr. selection between gpio and hi08 is made by clearing hpcr bits 6 through 1 for gpio or setting these bits for hi08 functionality. if the hi08 is in gpio mode, the hddr configures each corresponding signal in the hdr as an input signal if the hddr bit is cleared or as an output signal if the hddr bit is set. (see section 6.5.7?host data direction register (hddr) on page 6-17 and section 6.5.8?host data register (hdr) also on page 6-17.) 6.7 servicing the host interface the hi08 can be serviced by using one of the following protocols: polling interrupts the host processor writes to the appropriate hi08 register to reset the control bits and configure the hi08 for proper operation. 6.7.1 hi08 host processor data transfer to the host processor, the hi08 looks like a contiguous block of static ram. to transfer data between itself and the hi08, the host processor performs the following steps: 1. asserts the hi08 address to select the register to be read or written 2. selects the direction of the data transfer (if it is writing, the host processor sources the data on the bus.) 3. strobes the data transfer 6.7.2 polling in polling mode, the hreq/htrq signal is not connected to the host processor and hack must be deasserted to insure ivr data is not being driven on h[7:0] when other registers are being polled. (if the hack function is not needed, the hack signal can be configured as a gpio signal, as documented in section 6.5.6?host port control register (hpcr) on page 6-12.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-32 dsp56309um/d motorola host interface (hi08) servicing the host interface the host processor first performs a data read transfer to read the isr, as in figure 6-16 . this convention allows the host processor to assess the status of the hi08 and perform the appropriate actions. generally, after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. if rxdf is set, the receive data register is full, and the host processor can perform a data read. if txde is set, the transmit data register is empty, and the host processor can perform a data write. if trdy is set, the transmit data register is empty. this implies that the receive data register on the dsp side is also empty. data written by the host processor to the hi08 is transferred directly to the dsp side. if (hf2 and hf3) 1 0, depending on how the host flags have been used, this may indicate that an application-specific state within the dsp56309 has been reached. intervention by the host processor may be required. if hreq is set, the hreq/trq signal has been asserted, and the dsp56309 is requesting the attention of the host processor. one of the previous four conditions exists. after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. if the host processor has issued a command to the dsp56309 by writing to the cvr and setting the hc bit, it can read the hc bit in the cvr to determine whether the command has been accepted by the interrupt controller in the dsp core. when the command has been accepted for execution, the hc bit is cleared by the interrupt controller in the dsp core. 6.7.3 servicing interrupts if either hreq/htrq or the hrrq signal or both are connected to the host processor?s interrupt input, the hi08 can request service from the host processor by asserting one of these signals. the hreq/htrq and/or the hrrq signal is asserted when txde is set and/or rxdf is set and the corresponding enable bit (treq or rreq, respectively) is set. this situation appears in figure 6-16 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) servicing the host interface motorola dsp56309um/d 6-33 hreq is normally connected to the maskable interrupt input of the host processor. the host processor acknowledges host interrupts by executing an interrupt service routine. the host processor can test the two lsbs (rxdf and txde) of the isr register to determine the interrupt source, as in figure 6-16 . the host processor interrupt service routine must read or write the appropriate hi08 data register to clear the interrupt. hreq/htrq and/or hrrq is deasserted under either of the following conditions: the enabled request is cleared or masked. the dsp is reset. if the host processor is a member of the mc68000 family, there is no need for the additional step when the host processor reads the isr to determine how to respond to an interrupt generated by the dsp56309. instead, the dsp56309 automatically sources the contents of the ivr on the data bus when the host processor acknowledges the interrupt by asserting hack. the contents of the ivr are placed on the host data bus while hreq/trq (or hrrq) and hack are simultaneously asserted. the ivr data tells the mc680xx host processor which interrupt routine to execute to service the dsp56309. table 6-13 shows the hi08 programming model. figure 6-16 hi08 host request structure $0 hf1 hf0 hbend treq rreq icr enable 70 init 0 0 status 70 $2 hf3 hf2 trdy txde rxdf isr hreq 0 0 host request asserted hrrq hreq htrq aa0672 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-34 dsp56309um/d motorola host interface (hi08) hi08 programming model quick reference 6.8 hi08 programming model quick reference table 6-13 hi08 programming model reg bit comments reset type # mnemonic name value function hw/ sw i r s t dsp side hcr 0 hrie receive interrupt enable 0 1 hrrq interrupt disabled hrrq interrupt enabled ? 0?? 1 htie transmit interrupt enable 0 1 htrq interrupt disabled htrq interrupt enabled ? 0?? 2 hcie host command interrupt enable 0 1 hcp interrupt disabled hcp interrupt enabled ? 0?? 3 hf2 host flag 2 ?? ? 0?? 4 hf3 host flag 3 ?? ? 0?? hpcr 0 hgen host gpio enable 0 1 gpio signal disconnected gpio signals active ? 0?? 1 ha8en host address line 8 enable 0 1 ha8/a1 = gpio ha8/a1 = ha8 this bit is treated as 1 if hmux = 0. this bit is treated as 0 if hen = 0. 0?? 2 ha9en host address line 9 enable 0 1 ha9/a2 = gpio ha9/a2 = ha9 this bit is treated as 1 if hmux = 0. this bit is treated as 0 if hen = 0. 0?? 3 hcsen host chip select enable 0 1 hcs/a10 = gpio hcs/a10 = hcs this bit is treated as 0 if hen = 0. 0?? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 programming model quick reference motorola dsp56309um/d 6-35 hpcr 4 hren host request enable 0 1 hdrq = 0 hdrq = 1 hreq/htrq = gpio hreq/htrq hack/hrrq = gpio hreq/htrq = hreq,hreq/htrq hack/hrrq = htrq, hrrq ? 0?? 5 haen host acknowledge enable 0 1 hdrq = 0 hdrq=1 hack/hrrq = gpio hreq/htrq hack/hrrq = gpio hack/hrrq = hack hreq/htrq hack/hrrq = htrq, hrrq this bit is ignored if hdrq = 1. this bit is treated as 0 if hren = 0. this bit is treated as 0 if hen = 0. 0?? 6 hen host enable 0 1 host port = gpio host port active ? 0?? 8 hrod host request open drain 0 1 hreq/htrq/hrrq = driven hreq/htrq/hrrq = open drain this bit is ignored if hen = 0. 0 9 hdsp host data strobe polarity 0 1 hds/hrd/hwr active low hds/hrd/hwr active high this bit is ignored if hen = 0. 0?? 10 hasp host address strobe polarity 0 1 has active low has active high this bit is ignored if hen = 0. 0?? 11 hmux host multiplexed bus 0 1 separate address and data lines multiplexed address/data this bit is ignored if hen = 0. 0?? 12 hdds host dual data strobe 0 1 single data strobe (hds) double data strobe (hwr, hrd) this bit is ignored if hen = 0. 0?? table 6-13 hi08 programming model (continued) reg bit comments reset type # mnemonic name value function hw/ sw i r s t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-36 dsp56309um/d motorola host interface (hi08) hi08 programming model quick reference hpcr 13 hcsp host chip select polarity 0 1 hcs active low hcs active high this bit is ignored if hen = 0. 0?? 14 hrp host request polarity 0 1 hreq/htrq/hrrq active low hreq/htrq/hrrq active high this bit is ignored if hen = 0. 0?? 15 hap host acknowledge polarity 0 1 hack active low hack active high this bit is ignored if hen = 0. 0?? hsr 0 hrdf host receive data full 0 1 no receive data to be read receive data register is full ? 000 1 htde host transmit data empty 1 0 the transmit data register is empty. the transmit data register is not empty. ? 111 2 hcp host command pending 0 1 no host command pending host command pending ? 000 3 hf0 host flag 0 ?? ? 0?? 4 hf1 host flag 1 ?? ? 0?? hbar 7-0 ba10-ba3 host base address register ?? ? $80 ? ? hrx 23-0 ? dsp receive data register ?? ? empty ? ? htx 23-0 ? dsp transmit data register ?? ? empty ? ? hdr 16-0 d16-d0 gpio signal data ?? ? $0000 ? ? hdrr 16-0 dr16-dr0 gpio signal direction [0] [1] input output ? $0000 ? ? table 6-13 hi08 programming model (continued) reg bit comments reset type # mnemonic name value function hw/ sw i r s t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi08) hi08 programming model quick reference motorola dsp56309um/d 6-37 host side icr 0 rreq receive request enable 0 1 hrrq interrupt disabled hrrq interrupt enabled ? 0?? 1 treq transmit request enable 0 1 htrq interrupt disabled htrq interrupt enabled ? 0?? 2 hdrq double host request 0 1 hreq/htrq = hreq, hack/hrrq = hack hreq/htrq = htrq, hack/hrrq = hrrq ? 0?? 3 hf0 host flag 0 ?? ? 0?? 4 hf1 host flag 1 ?? ? 0?? 5 hlend host little endian 0 1 big endian order little endian order ? 0?? 7 init initialize 1 reset data paths according to treq and rreq cleared by hi08 hardware 0?? table 6-13 hi08 programming model (continued) reg bit comments reset type # mnemonic name value function hw/ sw i r s t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6-38 dsp56309um/d motorola host interface (hi08) hi08 programming model quick reference isr 0 rxdf receive data register full 0 1 host receive register is empty host receive register is full ? 000 1 txde transmit data register empty 1 0 host transmit register is empty host transmit register is full ? 111 2 trdy transmitter ready 1 0 transmit fifo (6 deep) is empty transmit fifo is not empty ? 111 3 hf2 host flag 2 ?? ? 0?? 4 hf3 host flag 3 ?? ? 0?? 7 hreq host request 0 1 hreq signal is deasserted hreq signal is asserted (if enabled) ? 000 cvr 6-0 hv6-hv0 host command vector ?? default vector via programmable $32 ? ? cvr 7 hc host command 0 1 no host command pending host command pending cleared by hi08 hardware when the hc interrupt request is serviced 000 rxh/m/l 7-0 ? host receive data register ?? ? empty ?? txh/m/l 7-0 ? host transmit data register ?? ? empty ? ? ivr 7-0 iv7-iv0 interrupt register ? 68000 family vector register ? $0f ? ? table 6-13 hi08 programming model (continued) reg bit comments reset type # mnemonic name value function hw/ sw i r s t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 7-1 section 7 enhanced synchronous serial interface (essi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-2 dsp56309um/d motorola enhanced synchronous serial interface (essi) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 enhancements to the essi . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 essi data and control signals . . . . . . . . . . . . . . . . 7-4 7.4 essi programming model . . . . . . . . . . . . . . . . . . . . . . 7-8 7.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7.6 gpio signals and registers. . . . . . . . . . . . . . . . . . . 7-43 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) introduction motorola dsp56309um/d 7-3 7.1 introduction the enhanced synchronous serial interface (essi) provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the motorola serial peripheral interface (spi). the essi consists of independent transmitter and receiver sections and a common essi clock generator. there are two independent and identical essis in the dsp56309: essi0 and essi1. for the sake of simplicity, a single generic essi is described. the essi block diagram appears in figure 7-1 on page 7-5. this interface is synchronous because all serial transfers are synchronized to a clock. note: this should not be confused with the asynchronous mode of the essi, in which separate clocks are used for the receiver and transmitter. in this mode, the essi is still a synchronous device, because all transfers are synchronized to these clocks. additional synchronization signals are used to delineate the word frames. normal mode is used to transfer data at a periodic rate, one word per period. network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. network mode can be used to build time division multiplexed (tdm) networks. in contrast, on-demand mode is intended for non-periodic transfers of data. this mode can be used to transfer data serially at high speed when the data become available. this mode offers a subset of the spi protocol. since each essi unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications (which need two digital input channels and six digital output channels). 7.2 enhancements to the essi the synchronous serial interface (ssi) used in the dsp56000 family has been enhanced in the following ways to make the essi: network enhancements e time slot mask registers (receive and transmit) added e end-of-frame interrupt added e drive enable signal added (to be used with transmitter 0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-4 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi data and control signals audio enhancements e three transmitters per essi (for six-channel surround sound) general enhancements e can trigger dma interrupts (receive or transmit) e separate exception enable bits other changes e one divide by 2 removed from the internal clock source chain e cra (psr) bit definition is reversed e gated clock mode not available 7.3 essi data and control signals three to six signals are required for essi operation, depending on the operating mode selected. the serial transmit data (std) signal and serial control (sc0 and sc1) signals are fully synchronized to the clock if they are programmed as transmit-data signals. 7.3.1 serial transmit data (std) signal the std signal is used for transmitting data from the tx0 serial transmit shift register. std is an output when data is being transmitted from the tx0 shift register. with an internally generated bit clock, the std signal becomes a high impedance output signal for a full clock period after the last data bit has been transmitted. if sequential data words are being transmitted, the std signal does not assume a high-impedance state. the std signal can be programmed as a gpio signal (p5) when the essi std function is not being used. 7.3.2 serial receive data signal (srd) the srd signal receives serial data and transfers the data to the essi receive shift register. srd can be programmed as a gpio signal (p4) when the essi srd function is not being used. the essi block diagram is shown in figure 7-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi data and control signals motorola dsp56309um/d 7-5 7.3.3 serial clock (sck) the sck signal is a bidirectional signal providing the serial bit rate clock for the essi interface. the sck signal is a clock input or output used by all the enabled transmitters and receiver in synchronous modes or by all the enabled transmitters in asynchronous figure 7-1 essi block diagram rsma rsmb tsma tsmb ssisr rx rx shift reg tx0 shift reg tsr rclk tx0 crb cra srd std tclk sc2 sck clock/frame sync generators and control logic interrupts gdb ddb tx1 shift reg tx1 sc0 tx2 shift reg tx2 sc1 aa0678 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-6 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi data and control signals modes; see table 7-1 on page 7-8. sck can be programmed as a gpio signal (p3) when the essi sck function is not being used. notes: 1. although an external serial clock can be independent of and asynchronous to the dsp system clock, the external essi clock frequency must not exceed f core /3, and each essi phase must exceed the minimum of 1.5 clkout cycles. 2. the internally sourced essi clock frequency must not exceed f core /4. 7.3.4 serial control signal (sc0) sc00 is a serial control signal for essi0, and sc10 is a serial control signal for essi1. they are referred to collectively as sc0. the function of this signal is determined by selecting either synchronous or asynchronous mode; see table 7-4 on page 7-24. in asynchronous mode, this signal is used for the receive clock i/o. in synchronous mode, this signal is used as the transmitter data out signal for transmit shift register 1 or for serial flag i/o. a typical application of serial flag i/o would be multiple device selection for addressing in codec systems. if sc0 is configured as a serial flag signal, its direction is determined by the serial control direction 0 (scd0) bit in the essi control register b (crb). when configured as an output, its value is determined by the value of the serial output flag 0 (of0) bit in the crb. when configured as an input, sc0 controls the state of serial input flag 0 (if0) bit in the essi status register (ssisr). when sc0 is configured as a transmit data signal, it is always an output signal regardless of the scd0 bit value. sc0 is fully synchronized with the other transmit data signals (std and sc1). in asynchronous mode, sc0 is configured as the receive clock. the direction of the sc0 in this mode is also determined by scd0. sc0 can be programmed as a gpio signal (p0) when the essi sc0 function is not being used. note: the essi can operate with more than one active transmitter only in synchronous mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi data and control signals motorola dsp56309um/d 7-7 7.3.5 serial control signal (sc1) sc01 is a serial control signal for essi0, and sc11 is a serial control signal for essi1. they are referred to collectively as sc1. the function of this signal is determined by selecting either synchronous or asynchronous mode; see table 7-4 on page 7-24. in asynchronous mode (such as a single codec with asynchronous transmit and receive), sc1 is the receiver frame sync i/o. in synchronous mode, sc1 is used for the transmitter data out signal of transmit shift register tx2, for the drive enable transmitter 0 signal, or for serial flag sc1. when used as a serial flag signal, sc1 operates like the previously described sc0. sc0 and sc1 are independent flags but can be used together for multiple serial device selection. sc0 and sc1 can be used unencoded to select up to two codecs or can be decoded externally to select up to four codecs. if sc1 is configured as a serial flag signal, its direction is determined by the scd1 bit in the crb. when configured as an output, its value is determined by the value of the serial output flag1 (of1) bit in the crb. when configured as an input, sc0 controls the stated serial input flag 1 (if1) bits in ssisr. when sc1 is configured as a transmit data signal, it is always an output signal regardless of the scd1 bit value. as an output, it is fully synchronized with the other essi transmit data signals (std and sc0). in asynchronous mode, sc1 is configured as the receive frame sync. the direction of sc1 in this mode is determined by scd1. sc1 can be programmed as a gpio signal (p1) when the essi sc1 function is not being used. table 7-1 summarizes essi clock sources, whether synchronous or asynchronous, and shows the bit settings for the signals involved. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-8 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.3.6 serial control signal (sc2) sc02 is a serial control signal for essi0, and sc12 is a serial control signal for essi1. they are referred to collectively as sc2. this signal is used for frame sync i/o. sc2 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. the direction of this signal is determined by the scd2 bit in the crb. when configured as an output, this signal outputs the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter in asynchronous mode and for the receiver when in synchronous mode. sc2 can be programmed as a gpio signal (p2) when the essi sc2 function is not being used. 7.4 essi programming model the essi includes the following registers: two control registers (cra, crb) illustrated in figure 7-2 and figure 7-3 one status register (ssisr) illustrated in figure 7-4 table 7-1 essi clock sources syn sckd scd0 r clock source rx clock out t clock source tx clock out asynchronous 0 0 0 ext, sc0 ? ext, sck ? 0 0 1 int sc0 ext, sck ? 0 1 0 ext, sc0 ? int sck 0 1 1 int sc0 int sck synchronous 1 0 0/1 ext, sck ? ext, sck ? 1 1 0/1 int sck int sck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-9 three transmit data registers (tx0, tx1, tx2) one receive data register (rx) two transmit slot mask registers (tsma, tsmb) illustrated in figure 7-5 and figure 7-6 two receive slot mask registers (rsma, rsmb) illustrated in figure 7-7 and figure 7-8 one special-purpose time slot register (tsr) the following paragraphs give detailed descriptions and operations of each of the bits in the essi registers. the gpio functionality of the essi is documented in section 7.6?gpio signals and registers of this manual. 11109876543210 psr pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 23 22 21 20 19 18 17 16 15 14 13 12 ssc1 wl2 wl1 wl0 alc dc4 dc3 dc2 dc1 dc0 aa0857 figure 7-2 essi control register a (cra) (essi0 x:$ffffb5, essi1 x:$ffffa5) 11109876543210 ckp fsp fsr fsl1 fsl0 shfd sckd scd2 scd1 scd0 of1 of0 23 22 21 20 19 18 17 16 15 14 13 12 reie teie rlie tlie rie tie re te0 te1 te2 mod syn aa0858 figure 7-3 essi control register b (crb) (essi0 x:$ffffb6, essi1 x:$ffffa6) 11109876543210 rdf tde roe tue rfs tfs if1 if0 23 22 21 20 19 18 17 16 15 14 13 12 aa0859 figure 7-4 essi status register (ssisr) (essi0 x:$ffffb7, essi1 x:$ffffa7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-10 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 11109876543210 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 23 22 21 20 19 18 17 16 15 14 13 12 ts15 ts14 ts13 ts12 aa0860 figure 7-5 essi transmit slot mask register a (tsma) (essi0 x:$ffffb4, essi1 x:$ffffa4) 11109876543210 ts27 ts26 ts25 ts24 ts23 ts22 ts21 ts20 ts19 ts18 ts17 ts16 23 22 21 20 19 18 17 16 15 14 13 12 ts31 ts30 ts29 ts28 aa0861 figure 7-6 essi transmit slot mask register b (tsmb) (essi0 x:$ffffb3, essi1 x:$ffffa3) 11109876543210 rs11 rs10 rs9 rs8 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 23 22 21 20 19 18 17 16 15 14 13 12 rs15 rs14 rs13 rs12 aa0862 figure 7-7 essi receive slot mask register a (rsma) (essi0 x:$ffffb2, essi1 x:$ffffa2) 11109876543210 rs27 rs26 rs25 rs24 rs23 rs22 rs21 rs20 rs19 rs18 rs17 rs16 23 22 21 20 19 18 17 16 15 14 13 12 rs31 rs30 rs29 rs28 e reserved bit - read as zero should be written with zero for future compatibility aa0863 figure 7-8 essi receive slot mask register b (rsmb) (essi0 x:$ffffb1, essi1 x:$ffffa1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-11 7.4.1 essi control register a (cra) the essi control register a (cra) is one of two 24-bit, read/write control registers used to direct the operation of the essi. the cra controls the essi clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. the cra control bits are described in the following paragraphs; see also figure 7-2 on page 7-9. 7.4.1.1 cra prescale modulus select pm[7:0] bits 7e0 the pm[7:0] bits specify the divide ratio of the prescale divider in the essi clock generator. a divide ratio from 1 to 256 (pm = $0 to $ff) can be selected. the bit clock output is available at the transmit clock signal (sck) and/or the receive clock (sc0) signal of the dsp. the bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. the essi clock generator functional diagram is shown in figure 7-9 . f core is the dsp56309 core clock frequency (the same frequency as the clkout signal, when that signal is enabled). careful choice of the crystal oscillator frequency and the prescaler modulus allows generation of the industry-standard codec master clock frequencies of 2.048 mhz, 1.544 mhz, and 1.536 mhz. both the hardware reset signal and the software reset instruction clear pm[7:0]. 7.4.1.2 cra reserved bits 8e10 these bits are reserved. they are read as 0 and should be written with 0. 7.4.1.3 cra prescaler range (psr) bit 11 the psr controls a fixed divide-by-eight prescaler in series with the variable prescaler. this bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. when psr is set, the fixed prescaler is bypassed. when psr is cleared, the fixed divide-by-eight prescaler is operational; see figure 7-9 on page 7-12. note: this definition is reversed from that of the 560xx ssi. the maximum allowed internally generated bit clock frequency is the internal dsp56309 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the dsp56309 internal clock frequency divided by 4096. both the hardware reset signal and the software reset instruction clear psr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-12 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model note: the combination psr = 1 and pm[7:0] = $00 (dividing f core by 2) can cause synchronization problems and should not be used. 7.4.1.4 cra frame rate divider control dc[4:0] bits 16e12 the values of the dc[4:0] bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks. in network mode, this ratio can be interpreted as the number of words per frame minus one. in normal mode, this ratio determines the word transfer rate. the divide ratio can range from 1 to 32 (dc = 00000 to 11111) for normal mode and 2 to 32 (dc = 00001 to 11111) for network mode. a divide ratio of one (dc = 00000) in network mode is a special case known as on-demand mode. in normal mode, a divide ratio of one (dc = 00000) provides continuous periodic data word transfers. a bit-length frame sync must be used in this case and is selected by setting the fsl[1:0] bits in the cra to (01). both the hardware reset signal and the software reset instruction clear dc[4:0]. the essi frame sync generator functional diagram is shown in figure 7-10 . figure 7-9 essi clock generator functional block diagram scn0 sckn crb(scd0) crb(sckd) crb(syn) = 1 scd0 = 0 rclock tclock internal bit clock syn = 1 cra(wl2:0) rx shift register tx shift register /1 or /8 /1 to /256 f core rx word clock syn = 0 scd0 = 1 note: 1. f core is the dsp56300 core internal clock frequency. 2. essi internal clock range: min = f osc /4096 max = f osc /4 3. ?n? in signal name is essi # (0 or 1) aa0679 sync: tx #1, or async: rx clk sync: tx/rx clk async: tx clk 0 0 0 255 cra(psr) cra(pm7:0) /8, /12, /16, /24, /32 1 2 3 4,5 flag0 out (sync mode) crb(of0) crb(te1) tx #1 flag0 in (sync mode) ssisr(if0) 1 syn = 0 0 /8, /12, /16, /24, /32 1 2 3 4,5 /2 cra(wl2:0) tx word clock flag0 (opposite from ssi) or f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-13 7.4.1.5 cra reserved bit 17 this bit is reserved. it is read as 0 and should be written with 0. 7.4.1.6 cra alignment control (alc) bit 18 the essi is designed for 24-bit fractional data. shorter data words are left aligned to the msb, bit 23. for applications that use 16 bit fractional data, shorter data words are left aligned to bit 15. the alc bit supports shorter data words. if alc is set, received words are left aligned to bit 15 in the receive shift register. transmitted words must be left aligned to bit 15 in the transmit shift register. if the alc bit is cleared, received words are left aligned to bit 23 in the receive shift register. transmitted words must be left aligned to bit 23 in the transmit shift register. the alc bit is cleared by either a hardware reset signal or a software reset instruction . note: if the alc bit is set, only 8-, 12-, or 16-bit words should be used. the use of 24- or 32-bit words leads to unpredictable results. figure 7-10 essi frame sync generator functional block diagram frame sync transmit frame sync receive rx word clock tx word clock cra(dc4:0) receive control logic transmit control logic sync type sync type crb(syn) = 0 syn = 1 internal rx frame sync crb(scd1) = 1 syn = 1 scd1 = 0 syn = 0 crb(scd1) internal tx frame sync aa0680 scn1 /1 to /32 31 0 crb(fsl1) crb(fsl1:0) cra(dc4:0) /1 to /32 31 0 scn2 crb(scd2) flag1 out, (sync mode) crb(of1) crb(te2) tx #2, or drive enb. cra(ssc1) flag1 in ssisr(if1) (sync mode) crb(fsr) sync: tx #2, async: rx f.s. flag1, or drive enb. sync: tx/rx f.s. async: tx f.s. crb(fsr) these signals are identical in sync mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-14 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.1.7 cra word-length control (wl[2:0]) bits 21e19 the wl[2:0] bits are used to select the length of the data words being transferred via the essi. word lengths of 8-, 12-, 16-, 24-, or 32- bits can be selected, as in table 7-2 . the essi data path programming model in figure 7-16 on page 7-31 and figure 7-17 on page 7-32 has additional information about selecting different length data words. the essi data registers are 24 bits long. the essi transmits 32-bit words either by duplicating the last bit eight times when wl[2:0] = 100, or by duplicating the first bit eight times when wl[2:0] = 101. the wl[2:0] bits are cleared by a hardware reset signal or by a software reset instruction. 7.4.1.8 cra select sc1 (ssc1) bit 22 the ssc1 bit controls the functionality of the sc1 signal. this bit is only valid when the essi is configured in synchronous mode (i.e., if the crb synchronous/asynchronous bit (syn) is set), and transmitter 2 is disabled (i.e., if transmit enable (te2) = 0). if ssc1 is set and sc1 is configured as an output (scd1 = 1), then the sc1 signal acts as the driver enabled signal of transmitter 0. this enables an external buffer for the transmitter 0 output. if ssc1 is cleared, sc1 acts as the serial i/o flag. 7.4.1.9 cra reserved bit 23 this bit is reserved. it is read as 0 and should be written with 0. table 7-2 essi word length selection wl2 wl1 wl0 number of bits/word 000 8 001 12 010 16 011 24 100 32 (valid data in the first 24 bits) 101 32 (valid data in the last 24 bits) 1 1 0 reserved 1 1 1 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-15 7.4.2 essi control register b (crb) the crb is one of two 24-bit, read/write control registers used to direct the operation of the essi; see figure 7-3 on page 7-9. crb controls the essi multifunction signals, sc[2:0], which can be used as clock inputs or outputs, frame synchronization signals, transmit data signals, or serial i/o flag signals. the serial output flag control bits and the direction control bits for the serial control signals are in the essi crb. interrupt enable bits for the receiver and the transmitter are also in the crb. the bit setting of the crb also determines how many transmitters are enabled (0, 1, 2, or 3 transmitters can be enabled). the crb settings also determine the essi operating mode. either a hardware reset signal or a software reset instruction clears all the bits in the crb. the relationship between the essi signals sc[2:0], sck, and the crb bits is summarized in table 7-4 on page 7-24. the essi crb bits are described in the following paragraphs. 7.4.2.1 crb serial output flags (of0, of1) bits 0, 1 the essi has two serial output flag bits, of1 and of0. the normal sequence for setting output flags when transmitting data (by transmitter 0 through the std signal only) consists of these steps: 1. wait for tde (tx0 empty) to be set. 2. write the flags. 3. write the transmit data to the tx register. bits of0 and of1 are double-buffered so that the flag states appear on the signals when the tx data is transferred to the transmit shift register. the flag bits values are synchronized with the data transfer. note: the timing of the optional serial output signals sc[2:0] is controlled by the frame timing and is not affected by the settings of te2, te1, te0, or the receive enable (re) bit of the crb. 7.4.2.1.1 crb serial output flag 0 (of0) bit 0 when the essi is in synchronous mode and transmitter 1 is disabled (te1 = 0), the sc0 signal is configured as essi flag 0. if the serial control direction bit (scd0) is set, the sc0 signal is an output. data present in bit of0 is written to sc0 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-16 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model bit of0 is cleared by a hardware reset signal or by a software reset instruction. 7.4.2.1.2 crb serial output flag 1 (of1) bit 1 when the essi is in synchronous mode and transmitter 2 is disabled (te2 = 0), the sc1 signal is configured as essi flag 1. if the serial control direction bit (scd1) is set, the sc1 signal is an output. data present in bit of1 is written to sc1 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. bit of1 is cleared by a hardware reset signal or by a software reset instruction. 7.4.2.2 crb serial control direction 0 (scd0) bit 2 in synchronous mode (syn = 1) when transmitter 1 is disabled (te1 = 0), or in asynchronous mode (syn = 0), scd0 controls the direction of the sc0 i/o signal. when scd0 is set, sc0 is an output; when scd0 is cleared, sc0 is an input. when te1 is set, the value of scd0 is ignored, and the sc0 signal is always an output. bit scd0 is cleared by a hardware reset signal or by a software reset instruction. 7.4.2.3 crb serial control direction 1 (scd1) bit 3 in synchronous mode (syn = 1) when transmitter 2 is disabled (te2 = 0), or in asynchronous mode (syn = 0), scd1 controls the direction of the sc1 i/o signal. when scd1 is set, sc1 is an output; when scd1 is cleared, sc1 is an input. when te2 is set, the value of scd1 is ignored, and the sc1 signal is always an output. bit scd1 is cleared by a hardware reset signal or by a software reset instruction. 7.4.2.4 crb serial control direction 2 (scd2) bit 4 scd2 controls the direction of the sc2 i/o signal. when scd2 is set, sc2 is an output; when scd2 is cleared, sc2 is an input. scd2 is cleared by a hardware reset signal or by a software reset instruction. 7.4.2.5 crb clock source direction (sckd) bit 5 sckd selects the source of the clock signal. if sckd is set and the essi is in synchronous mode, the internal clock is the source of the clock signal used for all the transmit shift registers and the receive shift register. if sckd is set and the essi is in asynchronous mode, the internal clock source becomes the bit clock for the transmit shift register and word length divider. the internal clock is output on the sck signal. when sckd is cleared, the external clock source is selected. the internal clock generator is disconnected from the sck signal, and an external clock source can drive this signal. either a hardware reset signal or a software reset instruction clears sckd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-17 7.4.2.6 crb shift direction (shfd) bit 6 the setting of the shfd bit determines the shift direction of the transmit or receive shift register. if shfd is set, data is shifted out with the lsb first. if shfd is cleared, data is shifted out msb first; see figure 7-16 on page 7-31 and figure 7-17 on page 7-32. received data is shifted in lsb first when shfd is set or msb first when shfd is cleared. either a hardware reset signal or a software reset instruction clears shfd. 7.4.2.7 crb frame sync length fsl[1:0] bits 7 and 8 these bits select the length of frame sync to be generated or recognized; see figure 7-11 on page 7-19, figure 7-14 on page 7-22, and figure 7-15 on page 7-23. the values of fsl[1:0] are documented in table 7-3 . the word length is defined by wl[2:0]. either a hardware reset signal or a software reset instruction clears fsl[1:0]. 7.4.2.8 crb frame sync relative timing (fsr) bit 9 the fsr bit determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines, for word length frame sync only. when fsr is cleared, the word length frame sync occurs together with the first bit of the data word of the first slot. when fsr is set, the word length frame sync occurs one serial clock cycle earlier (i.e., simultaneously with the last bit of the previous data word). either a hardware reset signal or a software reset instruction clears fsr. 7.4.2.9 crb frame sync polarity (fsp) bit 10 the fsp bit determines the polarity of the receive and transmit frame sync signals. when fsp is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated table 7-3 fsl1 and fsl0 encoding fsl1 fsl0 frame sync length rx tx 0 0 word word 0 1 word bit 1 0 bit bit 1 1 bit word f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-18 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model by the frame sync signal going high). when fsp is set, the frame sync signal polarity is negative (i.e., the frame start is indicated by the frame sync signal going low). either a hardware reset signal or a software reset instruction clears frb. 7.4.2.10 crb clock polarity (ckp) bit 11 the ckp bit controls on which bit clock edge data and frame sync are clocked out and latched in. if ckp is cleared, the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. if ckp is set, the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock. either a hardware reset signal or a software reset instruction clears ckp. 7.4.2.11 crb synchronous /asynchronous (syn) bit 12 syn controls whether the receive and transmit functions of the essi occur synchronously or asynchronously with respect to each other; see figure 7-12 on page 7-20. when syn is cleared, the essi is in asynchronous mode, and separate clock and frame sync signals are used for the transmit and receive sections. when syn is set, the essi is in synchronous mode and the transmit and receive sections use common clock and frame sync signals. only in synchronous mode can more than one transmitter be enabled. either a hardware reset signal or a software reset instruction clears syn. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-19 figure 7-11 crb fsl0 and fsl1 bit operation (fsr = 0) serial clock rx, tx frame sync word length: fsl1 = 0, fsl0 = 0 rx, tx serial data note: frame sync occurs while data is valid. data data serial clock rx, tx frame sync one bit length: fsl1 = 1, fsl0 = 0 rx, tx serial data note: frame sync occurs for one bit time preceding the data. serial clock tx frame sync mixed frame length: fsl1 = 0, fsl0 = 1 rx frame sync serial clock tx frame sync mixed frame length: fsl1 = 1, fsl0 = 1 tx serial data rx frame sync data data data data data data data data data data rxserial data tx serial data rx serial data aa0681 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-20 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.2.12 crb essi mode select (mod) bit 13 mod selects the operational mode of the essi; see figure 7-13 on page 7-21, figure 7-14 on page 7-22, and figure 7-15 on page 7-23. when mod is cleared, normal mode is selected; when mod is set, network mode is selected. in normal mode, the frame rate divider determines the word transfer rate: one word is transferred per frame sync during the frame sync time slot. in network mode, a word can be transferred every time slot. for more details, see section 7.5?operating modes . either a hardware reset signal or a software reset instruction clears mod. figure 7-12 crb syn bit operation external frame sync sc1 asynchronous (syn = 0) transmitter clock frame sync receiver clock frame sync srd std sc2 external transmit frame sync external receive frame sync internal frame sync sc0 sc external transmit clock external receive clock internal clock essi bit clock note: transmitter and receiver can have different clocks and frame syncs. synchronous (syn = 1) transmitter clock frame sync receiver clock frame sync srd std sc2 internal frame sync sck external clock internal clock essi bit clock note: transmitter and receiver can have the same clock frame syncs. aa0682 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-21 figure 7-13 crb mod bit operation ssi control register b (crb) (read/write) normal mode (mod = 0) serial clock frame sync serial data data data transmitter interrupt (or dma request) and flags set receiver interrupt (or dma request) and flags set note: interrupts occur and data is transferred once per frame sync. network mode (mod = 1) serial clock frame sync transmitter interrupts (or dma request) and flags set slot 1 slot 2 slot 3 slot 1 slot 2 serial data receiver interrupt (or dma request) and flags set note: interrupts occur every time slot and a word may be transferred. aa0683 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-22 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.2.13 enabling, disabling essi data transmission the essi has three transmit enable bits (te[2:0]), one for each data transmitter. the process of transmitting data from tx1 and tx2 is the same. tx0 can also operate in asynchronous mode. the normal transmit enable sequence is to write data to one or more transmit data registers (or the time slot register (tsr)) before setting the te bit. the normal transmit disable sequence is to clear the te, transmit interrupt enable (tie), and transmit exception interrupt enable (teie) bits after the transmit data empty (tde) bit is set. in network mode, clearing the appropriate te bit and setting it again disables the corresponding transmitter (0, 1, or 2) after transmission of the current data word. the transmitter remains disabled until the beginning of the next frame. during that time period, the corresponding sc (or std in the case of tx0) signal remains in the high-impedance state. 7.4.2.14 crb essi transmit 2 enable (te2) bit 14 the te2 bit enables the transfer of data from tx2 to transmit shift register 2. te2 is functional only when the essi is in synchronous mode and is ignored when the essi is in asynchronous mode. when te2 is set and a frame sync is detected, transmitter 2 is enabled for that frame. when te2 is cleared, transmitter 2 is disabled after completing transmission of data currently in the essi transmit shift register. any data present in tx2 is not transmitted. if te2 is cleared, data can be written to tx2; the tde bit is cleared, but data is not transferred to transmit shift register 2. figure 7-14 normal mode, external frame sync (8 bit, 1 word in frame) frame sync (fsl0 = 0, fsl1 = 0) frame sync (fsl0 = 0, fsl1 = 1) data out flags slot 0 slot 0 wait aa0684 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-23 keeping the te2 bit cleared until the start of the next frame causes the sc1 signal to act as serial i/o flag from the start of the frame, in both normal and network mode. the on-demand mode transmit enable sequence can be the same as normal mode, or the te2 bit can be left enabled. the te2 bit is cleared by either a hardware reset signal or a software reset instruction. note: the setting of the te2 bit does not affect the generation of frame sync or output flags. 7.4.2.15 crb essi transmit 1 enable (te1) bit 15 the te1 bit enables the transfer of data from tx1 to transmit shift register 1. te1 is functional only when the essi is in synchronous mode and is ignored when the essi is in asynchronous mode. when te1 is set and a frame sync is detected, the transmitter 1 is enabled for that frame. when te1 is cleared, transmitter 1 is disabled after completing transmission of data currently in the essi transmit shift register. any data present in tx1 is not transmitted. if te1 is cleared, data can be written to tx1; the tde bit is cleared, but data is not transferred to transmit shift register 1. keeping the te1 bit cleared until the start of the next frame causes the sc0 signal to act as serial i/o flag from the start of the frame, in both normal and network mode. the transmit enable sequence for on-demand mode can be the same as for normal mode, or the te1 bit can be left enabled. figure 7-15 network mode, external frame sync (8 bit, 2 words in frame) slot 0 slot 1 slot 1 slot 0 frame sync (fsl0 = 0, fsl1 = 0) frame sync (fsl0 = 0, fsl1 = 1) flags data aa1593 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-24 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model the te1 bit is cleared by either a hardware reset signal or a software reset instruction. note: the setting of the te1 bit does not affect the generation of frame sync or output flags. 7.4.2.16 crb essi transmit 0 enable (te0) bit 16 the te0 bit enables the transfer of data from tx0 to transmit shift register 0. te0 is functional when the essi is in either synchronous or asynchronous mode. when te0 is set and a frame sync is detected, the transmitter 0 is enabled for that frame. when te0 is cleared, transmitter 0 is disabled after completing transmission of data currently in the essi transmit shift register. the std output is tri-stated, and any data present in tx0 is not transmitted (i.e., data can be written to tx0 with te0 cleared; the tde bit is cleared, but data is not transferred to the transmit shift register 0). the te0 bit is cleared by either a hardware reset signal or a software reset instruction. the transmit enable sequence for on-demand mode can be the same as for normal mode, or te0 can be left enabled. note: transmitter 0 is the only transmitter that can operate in asynchronous mode (syn = 0). te0 does not affect the generation of frame sync or output flags. table 7-4 summarizes the preceding sections; it shows possible settings of control bits and their associated signals. table 7-4 mode and signal definition table control bits essi signals syn te0 te1 te2 re sc0 sc1 sc2 sck std srd 00xx0u u uuuu 0 0 x x 1 rxc fsr u u u rd 0 1 x x 0 u u fst txc td0 u 0 1 x x 1 rxc fsr fst txc td0 rd 10000u u uuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-25 1 0 0 0 1 f0/u f1/t0d/u fs xc u rd 1 0 0 1 0 f0/u td2 fs xc u u 1 0 0 1 1 f0/u td2 fs xc u rd 1 0 1 0 0 td1 f1/t0d/u fs xc u u 1 0 1 0 1 td1 f1/t0d/u fs xc u rd 1 0 1 1 0 td1 td2 fs xc u u 1 0 1 1 1 td1 td2 fs xc u rd 1 1 0 0 0 f0/u f1/t0d/u fs xc td0 u 1 1 0 0 1 f0/u f1/t0d/u fs xc td0 rd 1 1 0 1 0 f0/u td2 fs xc td0 u 1 1 0 1 1 f0/u td2 fs xc td0 rd 1 1 1 0 0 td1 f1/t0d/u fs xc td0 u 1 1 1 0 1 td1 f1/t0d/u fs xc td0 rd 1 1 1 1 0 td1 td2 fs xc td0 u 1 1 1 1 1 td1 td2 fs xc td0 rd note: txc = transmitter clock note: rxc = receiver clock note: xc = transmitter/receiver clock (synchronous operation) note: fst = transmitter frame sync note: fsr = receiver frame sync note: fs = transmitter/receiver frame sync (synchronous operation) note: td0 = transmit data signal 0 note: td1 = transmit data signal 1 note: td2 = transmit data signal 2 note: t0d = transmitter 0 drive enable if ssc1 = 1 & scd1 = 1 note: rd = receive data note: f0 = flag 0 note: f1 = flag 1 if ssc1 = 0 note: u = unused (can be used as gpio signal) note: x = indeterminate table 7-4 mode and signal definition table (continued) control bits essi signals syn te0 te1 te2 re sc0 sc1 sc2 sck std srd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-26 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.2.17 crb essi receive enable (re) bit 17 when the re bit is set, the receive portion of the essi is enabled. when this bit is cleared, the receiver is disabled by inhibiting data transfer into rx. if data is being received while this bit is cleared, the remainder of the word is shifted in and transferred to the essi receive data register. re must be set in both the normal and on-demand modes for the essi to receive data. in network mode, clearing re and setting it again disables the receiver after reception of the current data word. the receiver remains disabled until the beginning of the next data frame. re is cleared by either a hardware reset signal or a software reset instruction. note: the setting of the re bit does not affect the generation of a frame sync. 7.4.2.18 crb essi transmit interrupt enable (tie) bit 18 setting the tie bit enables a dsp transmit interrupt, which is generated when both the tie and the tde bits in the essi status register are set. when tie is cleared, the transmit interrupt is disabled. the use of the transmit interrupt is described in section 7.5.3 . writing data to the data registers of the enabled transmitters or to the tsr clears tde and also clears the interrupt. transmit interrupts with exception conditions have higher priority than normal transmit data interrupts. if the transmitter underrun error (tue) bit is set, signaling that an exception has occurred, and the teie bit is set, the essi requests an ssi transmit data with exception interrupt from the interrupt controller. tie is cleared by either a hardware reset signal or a software reset instruction. 7.4.2.19 crb essi receive interrupt enable (rie) bit 19 setting the rie enables a dsp receive data interrupt, which is generated when both the rie and receive data register full (rdf) bit in the ssisr are set. when rie is cleared, this interrupt is disabled. the use of the receive interrupt is described in section 7.5.3 . reading the receive data register clears rdf and the pending interrupt. receive interrupts with exception have higher priority than normal receive data interrupts. if the receiver overrun error (roe) bit is set, signaling that an exception has occurred, and the reie bit is set, the essi requests an ssi receive data with exception interrupt from the interrupt controller. rie is cleared by either a hardware reset signal or a software reset instruction. 7.4.2.20 transmit last slot interrupt enable (tlie) bit 20 setting the tlie bit enables an interrupt at the beginning of the last slot of a frame when the essi is in network mode. when tlie is set, the dsp is interrupted at the start of the last slot in a frame regardless of the transmit mask register setting. when tlie is cleared, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-27 the transmit last slot interrupt is disabled. the use of the transmit last slot interrupt is described in section 7.5.3?essi exceptions . tlie is cleared by either a hardware reset signal or a software reset instruction. tlie is disabled when the essi is in on-demand mode (dc = $0). 7.4.2.21 receive last slot interrupt enable (rlie) bit 21 setting the rlie bit enables an interrupt after the last slot of a frame ends when the essi is in network mode. when rlie is set, the dsp is interrupted after the last slot in a frame ends regardless of the receive mask register setting. when rlie is cleared, the receive last slot interrupt is disabled. the use of the receive last slot interrupt is described in section 7.5.3?essi exceptions . rlie is cleared by either a hardware reset signal or a software reset instruction. rlie is disabled when the essi is in on-demand mode (dc = $0). 7.4.2.22 transmit exception interrupt enable (teie) bit 22 when the teie bit is set, the dsp is interrupted when both tde and tue in the essi status register are set. when teie is cleared, this interrupt is disabled. the use of the transmit interrupt is described in section 7.5.3?essi exceptions . reading the status register, followed by writing to all the data registers of the enabled transmitters, clears both tue and the pending interrupt. teie is cleared by either a hardware reset signal or a software reset instruction. 7.4.2.23 receive exception interrupt enable (reie) bit 23 when the reie bit is set, the dsp is interrupted when both rdf and roe in the essi status register are set. when reie is cleared, this interrupt is disabled. the use of the receive interrupt is described in section 7.5.3?essi exceptions . reading the status register followed by reading the receive data register clears both roe and the pending interrupt. reie is cleared by either a hardware reset signal or a software reset instruction. 7.4.3 essi status register (ssisr) the ssisr (in figure 7-4 on page 7-9) is a 24-bit, read-only status register used by the dsp to read the status and serial input flags of the essi. the ssisr bits are documented in the following paragraphs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-28 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.3.1 ssisr serial input flag 0 (if0) bit 0 the if0 bit is enabled only when sc0 is an input flag and synchronous mode is selected (i.e., when the syn bit is set, and the te1 and scd0 bits are cleared). the essi latches data present on the sc0 signal during reception of the first received bit after the frame sync is detected. the if0 bit is updated with this data when the data in the receive shift register is transferred into the receive data register. if it is not enabled, the if0 bit is cleared. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears the if0 bit. 7.4.3.2 ssisr serial input flag 1 (if1) bit 1 the if1 bit is enabled only when sc1 is an input flag and synchronous mode is selected, the syn bit is set, and the te2 and scd1 bits are cleared. the essi latches data present on the sc1 signal during reception of the first received bit after the frame sync is detected. the if1 bit is updated with this data when the data in the receive shift register is transferred into the receive data register. if it is not enabled, the if1 bit is cleared. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears the if1 bit. 7.4.3.3 ssisr transmit frame sync flag (tfs) bit 2 when set, tfs indicates that a transmit frame sync occurred in the current time slot. tfs is set at the start of the first time slot in the frame and cleared during all other time slots. if the transmitter is enabled, data written to a transmit data register during the time slot when tfs is set is transmitted (in network mode) during the second time slot in the frame. tfs is useful in network mode to identify the start of a frame. tfs is valid only if at least one transmitter is enabled (te0, te1 or te2 are set). a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears tfs. note: in normal mode, tfs is always read as 1 when transmitting data because there is only one time slot per frame, the ?frame sync? time slot. 7.4.3.4 ssisr receive frame sync flag (rfs) bit 3 when set, the rfs bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register. this means that the data word is from the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-29 first time slot in the frame. when the rfs bit is cleared and a word is received, it indicates (only in network mode) that the frame sync did not occur during reception of that word. rfs is valid only if the receiver is enabled (i.e., the re bit is set). a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears rfs. note: in normal mode, rfs is always read as 1 when reading data because there is only one time slot per frame, the frame sync time slot. 7.4.3.5 ssisr transmitter underrun error flag (tue) bit 4 the tue bit is set when at least one of the enabled serial transmit shift registers is empty (no new data to be transmitted) and a transmit time slot occurs. when a transmit underrun error occurs, the previous data (which is still present in the tx registers that were not written) is retransmitted. in normal mode, there is only one transmit time slot per frame. in network mode, there can be up to thirty-two transmit time slots per frame. if the teie bit is set, a dsp transmit underrun error interrupt request is issued when the tue bit is set. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears tue. tue can also be cleared by first reading the ssisr with the tue bit set, then writing to all the enabled transmit data registers or to the tsr. 7.4.3.6 ssisr receiver overrun error flag (roe) bit 5 the roe bit is set when the serial receive shift register is filled and ready to transfer to the receive data register (rx), but rx is already full (i.e., the rdf bit is set). if the reie bit is set, a dsp receiver overrun error interrupt request is issued when the roe bit is set. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears roe. roe can also be cleared by reading the ssisr with the roe bit set and then reading the rx. 7.4.3.7 essi transmit data register empty (tde) bit 6 the tde bit is set when the contents of the transmit data register of every enabled transmitter are transferred to the transmit shift register. it is also set for a tsr disabled time slot period in network mode (as if data were being transmitted after the tsr was written). when set, the tde bit indicates that data should be written to all the tx registers of the enabled transmitters or to the tsr. the tde bit is cleared when the dsp56309 writes to all the transmit data registers of the enabled transmitters or when the dsp writes to the tsr to disable transmission of the next time slot. if the tie bit is set, a dsp transmit data interrupt request is issued when tde is set. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears the tde bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-30 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.3.8 essi receive data register full (rdf) bit 7 the rdf bit is set when the contents of the receive shift register are transferred to the receive data register. the rdf bit is cleared when the dsp reads the receive data register. if rie is set, a dsp receive data interrupt request is issued when rdf is set. a hardware reset signal, software reset instruction, essi individual reset, or stop instruction clears the rdf bit. the essi data path programming models are shown in figure 7-16 on page 7-31 and figure 7-17 on page 7-32. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-31 figure 7-16 essi data path programming model (shfd = 0) srd essi receive data register (read only) serial receive shift register 24 bit wl1, wl0 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb least significant zero fill notes: data is received msb first if shfd = 0. 24-bit fractional format (alc = 0). 32-bit mode is not shown. 16 bit 12 bit 8 bit (a) receive registers std essi transmit data register (write only) essi transmit shift register 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb least significant zero fill (b) transmit registers transmit high byte transmit middle byte transmit low byte transmit high byte transmit middle byte transmit low byte 23 16 15 8 7 0 23 16 15 8 70 707 0 70 7070 7 0 msb msb msb notes: data is transmitted msb first if shfd = 0. 4-bit fractional format (alc = 0). 32-bit mode is not shown. receive high byte receive middle byte receive low byte receive high byte receive middle byte receive low byte 23 16 15 87 0 23 16 15 70 707 7 0 7070 7 0 msb msb msb msb aa0686 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-32 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model figure 7-17 essi data path programming model (shfd = 1) srd essi receive data register (read only) essi receive shift register 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill (a) receive registers std essi transmit data register (write only) essi transmit shift register 24 bit wl1, wl0 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill 16 bit 12 bit 8 bit (b) transmit registers receive high byte receive middle byte receive low byte receive high byte receive middle byte receive low byte 23 16 15 87 0 23 16 15 7 0 707 7 0 70707 0 notes: data is received msb first if shfd = 0. 24-bit fractional format (alc = 0). 32-bit mode is not shown. transmit high byte transmit middle byte transmit low byte transmit high byte transmit middle byte transmit low byte 23 16 15 8 7 0 23 16 15 7 0 707 7 0 70707 0 notes: data is received msb first if shfd = 0. 4-bit fractional format (alc = 0). 32-bit mode is not shown. 0 0 aa0687 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-33 7.4.4 essi receive shift register the 24-bit receive shift register (in figure 7-16 on page 7-31 and figure 7-17 on page 7-32) receives the incoming data from the serial receive data signal. data is shifted in by the selected (internal/external) bit clock when the associated frame sync i/o is asserted. it is assumed that data is received msb first if shfd is cleared and lsb first if shfd is set. data is transferred to the essi receive data register after 8, 12, 16, 24, or 32 serial clock cycles are counted, depending on the word-length control bits in the cra. 7.4.5 essi receive data register (rx) the receive data register (rx) is a 24-bit, read-only register that accepts data from the receive shift register as it becomes full; see figure 7-16 on page 7-31 and figure 7-17 on page 7-32. the data read is aligned according to the value of the alc bit. when the alc bit is cleared, the msb is bit 23 and the least significant byte is unused. when the alc bit is set, the msb is bit 15 and the most significant byte is unused. unused bits are read as 0s. if the associated interrupt is enabled, the dsp is interrupted whenever the rx register becomes full. 7.4.6 essi transmit shift registers the three 24-bit transmit shift registers contain the data being transmitted; see figure 7-16 on page 7-31 and figure 7-17 on page 7-32. data is shifted out to the serial transmit data signals by the selected (internal/external) bit clock when the associated frame sync i/o is asserted. the word-length control bits in the cra determine the number of bits that must be shifted out before the shift registers are considered empty and can be written to again. depending on the setting of the cra, the number of bits to be shifted out can be 8, 12, 16, 24, or 32 bits. the data transmitted is aligned according to the value of the alc bit. when the alc bit is cleared, the msb is bit 23 and the least significant byte is unused. when alc is set, the msb is bit 15 and the most significant byte is unused. unused bits are read as 0s. data is shifted out of these registers msb first if the shfd bit is cleared and lsb first if the shfd bit is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-34 dsp56309um/d motorola enhanced synchronous serial interface (essi) essi programming model 7.4.7 essi transmit data registers (tx0-2) tx20, tx10, and tx00 are transmit data registers for essi0. tx21, tx11, and tx01 are transmit data registers for essi1. tx20 and tx21 are known as tx2. tx10 and tx11 are known as tx1. tx00 and tx01 are known as tx0. tx2, tx1, and tx0 are 24-bit, write-only registers. data to be transmitted is written into these registers and automatically transferred to the transmit shift registers; see figure 7-16 on page 7-31 and figure 7-17 on page 7-32. the data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the alc bit. when the alc bit is cleared, the msb is bit 23. when alc is set, the msb is bit 15. if the transmit data register empty interrupt has been enabled, the dsp is interrupted whenever a transmit data register becomes empty. note: when data is written to a peripheral device, there is a two cycle pipeline delay until any status bits affected by this operation are updated. if you read any of those status bits within the next two cycles, the bit does not reflect its current status. see the dsp56300 family manual, appendix b, polling a peripheral device for write for further details. 7.4.8 essi time slot register (tsr) tsr is effectively a write-only null data register that is used to prevent data transmission in the current transmit time slot. for the purposes of timing, tsr is a write-only register that behaves like an alternative transmit data register, except that, rather than transmitting data, the transmit data signals of all the enabled transmitters are in the high-impedance state for the current time slot. 7.4.9 transmit slot mask registers (tsma, tsmb) the transmit slot mask registers are two 16-bit, read/write registers. when the tsma or tsmb is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled. in network mode, these registers are used by the transmitter(s) to determine what action to take in the current transmission slot. depending on the setting of the bits, the transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data word and generate a transmitter empty condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) essi programming model motorola dsp56309um/d 7-35 tsma and tsmb (in figure 7-16 on page 7-31 and figure 7-17 on page 7-32) can be seen as a single 32-bit register, tsm. bit n in tsm (tsn) is an enable/disable control bit for transmission in slot number n. when tsn is cleared, all the transmit data signals of the enabled transmitters are tri-stated during transmit time slot number n. the data is still transferred from the enabled transmit data register(s) to the transmit shift register. however, the tde and the tue flags are not set. this means that during a disabled slot, no transmitter empty interrupt is generated. the dsp is interrupted only for enabled slots. data written to the transmit data register when servicing the transmitter empty interrupt request is transmitted in the next enabled transmit time slot. when tsn is set, the transmit sequence proceeds normally. data is transferred from the tx register to the shift register during slot number n and the tde flag is set. using the tsm slot mask does not conflict with using the tsr. even if a slot is enabled in the tsm, you can write to the tsr to tri-state the signals of the enabled transmitters during the next transmission slot. setting the bits in the tsm affects the next frame transmission. the frame currently being transmitted is not affected by the new tsm setting. if the tsm is read, it shows the current setting. after a hardware reset signal or software reset instruction, the tsm register is reset to $ffffffff; this setting enables all thirty-two slots for data transmission. 7.4.10 receive slot mask registers (rsma, rsmb) the receive slot mask registers are two 16-bit, read/write registers. in network mode, these registers are used by the receiver(s) to determine what action to take in the current time slot. depending on the setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and generate a receiver full condition. rsma and rsmb (in figure 7-16 on page 7-31 and figure 7-17 on page 7-32) can be seen as one 32-bit register, rsm. bit n in rsm (rsn) is an enable/disable control bit for time slot number n. when rsn is cleared, all the data signals of the enabled receivers are tri-stated during time slot number n. data is transferred from the receive data register(s) to the receive shift register(s) and the rdf and roe flags are not set. during a disabled slot, no receiver full interrupt is generated. the dsp is interrupted only for enabled slots. when rsn is set, the receive sequence proceeds normally. data is received during slot number n, and the rdf flag is set. setting the bits in the rsm affects the next frame transmission. the frame currently being transmitted is not affected by the new rsm setting. if the rsm is read, it shows the current setting. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-36 dsp56309um/d motorola enhanced synchronous serial interface (essi) operating modes when the rsma or rsmb register are read by the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled. after a hardware reset signal or a software reset instruction, the rsm register is reset to $ffffffff; this setting enables all thirty-two time slots for data transmission. 7.5 operating modes the essi operating modes are selected by the essi control registers (cra and crb). the operating modes are described in the following paragraphs. 7.5.1 essi after reset a hardware reset signal or software reset instruction clears the port control register and the port direction control register. this situation configures all the essi signals as gpio. the essi is in the reset state while all essi signals are programmed as gpio; the essi is active only if at least one of the essi i/o signals is programmed as an essi signal. 7.5.2 essi initialization to initialize the essi, do the following: 1. send a reset: a hardware reset signal, software reset instruction, essi individual reset, or stop instruction. 2. program the essi control and time slot registers. 3. write data to all the enabled transmitters. 4. configure at least one signal as an essi signal. 5. if an external frame sync is used, from the moment the essi is activated, at least five serial clocks are needed before the first external frame sync is supplied. otherwise, improper operation can result. clearing the pc[5:0] bits in the gpio pcr during program execution causes the essi to stop serial activity and enter the individual reset state. all status bits of the interface are set to their reset state. the contents of cra and crb are not affected. the essi individual reset allows a program to reset each interface separately from the other f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) operating modes motorola dsp56309um/d 7-37 internal peripherals. during essi individual reset, internal dma accesses to the data registers of the essi are not valid and data read is undefined. to insure proper operation of the essi, use an essi individual reset when changing the essi control registers (except for bits teie, reie, tlie, rlie, tie, rie, te2, te1, te0, and re). here is an example of initializing the essi. 1. put the essi in its individual reset state by clearing the pcr bits. 2. configure the control registers (cra, crb) to set the operating mode. disable the transmitters and receiver by clearing the te[2:0] and re bits. set the interrupt enable bits for the operating mode chosen. 3. enable the essi by setting the pcr bits to activate the input/output signals to be used. 4. write initial data to the transmitters that are used during operation. this step is needed even if dma is used to service the transmitters. 5. enable the transmitters and receiver to be used. now the essi can be serviced by polling, interrupts, or dma. once the essi has been enabled (step 3), operation starts as follows: for internally generated clock and frame sync, these signals start activity immediately after the essi is enabled. data is received by the essi after the occurrence of a frame sync signal (either internally or externally generated) only when the receive enable (re) bit is set. data is transmitted after the occurrence of a frame sync signal (either internally or externally generated) only when the transmitter enable (te[2:0]) bit is set. 7.5.3 essi exceptions the essi can generate six different exceptions. they are discussed in the following paragraphs (ordered from the highest to the lowest exception priority) : 1. essi receive data with exception status: occurs when the receive exception interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. this exception sets the roe bit. the roe bit is cleared by first reading the ssisr and then reading rx. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-38 dsp56309um/d motorola enhanced synchronous serial interface (essi) operating modes 2. essi receive data: occurs when the receive interrupt is enabled, the receive data register is full, and no receive error conditions exist. reading rx clears the pending interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead. 3. essi receive last slot interrupt: occurs when the essi is in network mode and the last slot of the frame has ended. this interrupt is generated regardless of the receive mask register setting. the receive last slot interrupt can be used to signal that the receive mask slot register can be reset, the dma channels can be reconfigured, and data memory pointers can be reassigned. using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems. note: the maximum time it takes to service a receive last slot interrupt should not exceed n e 1 essi bits service time (where n is the number of bits the essi can transmit per time slot). 4. essi transmit data with exception status: occurs when the transmit exception interrupt is enabled, at least one transmit data register of the enabled transmitters is empty, and a transmitter underrun error has occurred. this exception sets the tue bit. the tue bit is cleared by first reading the ssisr and then writing to all the transmit data registers of the enabled transmitters or by writing to the tsr to clear the pending interrupt. 5. essi transmit last slot interrupt: occurs when the essi is in network mode at the start of the last slot of the frame. this exception occurs regardless of the transmit mask register setting. the transmit last slot interrupt can be used to signal that the transmit mask slot register can be reset, the dma channels can be reconfigured, and data memory pointers can be reassigned. using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting, and the new frame is serviced with the new setting without synchronization problems. note: the maximum transmit last slot interrupt service time should not exceed n e 1 essi bits service time (where n is the number of bits in a slot). 6. essi transmit data: occurs when the transmit interrupt is enabled, at least one of the enabled transmit data registers is empty, and no transmitter error conditions exist. writing to all the enabled tx registers or to the tsr clears this interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead (if no more than two transmitters are used). to configure an essi exception, perform the following steps: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) operating modes motorola dsp56309um/d 7-39 1. configure interrupt service routine (isr) a. load vector base address register. vba (b23:8) b. define i_vec to be equal to the vba value (if that is nonzero). if it is defined, i_vec must be defined for the assembler before the interrupt equate file is included. c. load the exception vector table entry: two-word fast interrupt or jump/branch to subroutine (long interrupt). p:i_si0td 2. configure interrupt trigger/preload transmit data a. enable and prioritize overall peripheral interrupt functionality. iprp (s0l1:0) b. enable peripheral and associated signals. pcrc (pc5:0) c. write data to all enabled transmit registers. tx00 d. enable peripheral interrupt-generating function. crb (te0) e. enable specific peripheral interrupt. crb0 (tie) f. unmask interrupts at global level. sr (i1:0) notes: 1. the example material to the right of the steps above shows register settings for configuring an essi0 transmit interrupt using transmitter 0. 2. the order of the steps is optional except that the interrupt trigger configuration must not be completed until the isr configuration has been completed. since 2d can cause an immediate transmit without generating an interrupt, perform the transmit data preload in 2c before 2d to insure valid data is sent in the first transmission. 3. after the first transmit, subsequent transmit values are typically loaded into txnn by the isr (one value per register per interrupt). therefore, if n items are to be sent from a particular txnn, the isr will need to load the transmit register (n e 1) times. 4. steps d and e can be performed using a single instruction. 5. if an interrupt trigger event occurs at a time when not all interrupt trigger configuration steps have been performed, the event is ignored forever (the event is not queued in this case). 6. if interrupts derived from the core or other peripherals need to be enabled at the same time as essi interrupts, step f should be done last. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-40 dsp56309um/d motorola enhanced synchronous serial interface (essi) operating modes 7.5.4 operating modes: normal, network, and on-demand the essi has three basic operating modes and several data/operation formats. these modes can be programmed using the essi control registers. the data/operation formats available to the essi are selected by setting or clearing control bits in the cra and crb. these control bits are wl[2:1], mod, syn, fsl[1:0], fsr, fsp, ckp, and shfd. 7.5.4.1 normal/network/on-demand mode selection to select normal mode (or network mode), clear (or set) the mod bit in the crb. in normal mode, the essi sends or receives one data word per frame (per enabled receiver or transmitter). in network mode, two to thirty-two time slots per frame can be selected. during each frame, zero to thirty-two data words can be received or transmitted (from each enabled receiver or transmitter). in either case, the transfers are periodic. normal mode is typically used to transfer data to or from a single device. network mode is typically used in tdm networks of codecs or dsps with multiple words per frame. network mode has a sub-mode called on-demand mode. setting the mod bit in the crb for network mode, and setting the frame rate divider to 0 (dc = $00000) selects the on-demand mode. this sub-mode does not generate a periodic frame sync. a frame sync pulse is generated only when data is available to transmit. the frame sync signal indicates the first time slot in the frame. the on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). for simplex operation, synchronous mode could be used; however, for full-duplex operation, asynchronous mode must be used. data transmission that is data driven is enabled by writing data into each tx. although the essi is double-buffered, only one word can be written to each tx, even if the transmit shift register is empty. the receive and transmit interrupts function normally, using tde and rdf; however, transmit underruns are impossible for ?on- demand? transmission and are disabled. this mode is useful for interfacing to codecs requiring a continuous clock. 7.5.4.2 synchronous/asynchronous operating modes the transmit and receive sections of the essi interface can be synchronous or asynchronous. the transmitter and receiver use common clock and synchronization signals in synchronous mode; they use separate clock and sync signals in asynchronous mode. the syn bit in crb selects synchronous or asynchronous operation. when the syn bit is cleared, the essi tx and rx clocks and frame sync sources are independent. if the syn bit is set, the essi tx and rx clocks and frame sync are driven by the same source (either external or internal). since the essi is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) operating modes motorola dsp56309um/d 7-41 transmitter 1 and transmitter 2 operate only in synchronous mode. data clock and frame sync signals can be generated internally by the dsp or can be obtained from external sources. if clocks are internally generated, the essi clock generator derives bit clock and frame sync signals from the dsp internal system clock. the essi clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame-rate divider with a word-length divider for frame-rate sync-signal generation. 7.5.4.3 frame sync selection the transmitter and receiver can operate independently. the transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or another format. the selection is made by programming fsl[1:0], fsr, and fsp bits in the crb. 7.5.4.3.1 frame sync signal format fsl1 controls the frame-sync signal format. if the fsl1 bit is cleared, the rx frame sync is asserted during the entire data transfer period. this frame sync length is compatible with motorola codecs, serial peripherals that conform to the motorola spi, serial a/d and d/a converters, shift registers, and telecommunication pulse code modulation (pcm) serial i/o. if the fsl1 bit is set, the rx frame sync pulses active for one bit clock immediately before the data transfer period. this frame sync length is compatible with intel and national components, codecs, and telecommunication pcm serial i/o. 7.5.4.3.2 frame sync length for multiple devices the ability to mix frame sync lengths is useful in configuring systems in which data is received from one type of device (e.g., codec) and transmitted to a different type of device. fsl0 controls whether rx and tx have the same frame sync length. if the fsl0 bit is cleared, both rx and tx have the same frame sync length. if the fsl0 bit is set, rx and tx have different frame sync lengths. fsl0 is ignored when the syn bit is set. 7.5.4.3.3 word-length frame sync and data-word timing the fsr bit controls the relative timing of the word-length frame sync relative to the data word timing. when the fsr bit is cleared, the word length frame sync is generated (or expected) with the first bit of the data word. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-42 dsp56309um/d motorola enhanced synchronous serial interface (essi) operating modes when the fsr bit is set, the word length frame sync is generated (or expected) with the last bit of the previous word. fsr is ignored when a bit length frame sync is selected. 7.5.4.3.4 frame sync polarity the fsp bit controls the polarity of the frame sync. when the fsp bit is cleared, the polarity of the frame sync is positive (i.e., the frame sync signal is asserted high). the essi synchronizes on the leading edge of the frame sync signal. when the fsp bit is set, the polarity of the frame sync is negative (i.e., the frame sync is asserted low). the essi synchronizes on the trailing edge of the frame sync signal. the essi receiver looks for a receive frame sync edge (leading edge if fsp is cleared, trailing edge if fsp is set) only when the previous frame is completed. if the frame sync is asserted before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with fsr set), the current frame sync is not recognized, and the receiver is internally disabled until the next frame sync. frames do not have to be adjacent, that is, a new frame sync does not have to follow immediately the previous frame. gaps of arbitrary periods can occur between frames. all the enabled transmitters are tri-stated during these gaps. 7.5.4.4 byte format (lsb/msb) for the transmitter some devices, such as codecs, require a msb-first data format. other devices, such as those that use the aes-ebu digital audio format, require the lsb first. to be compatible with all formats, the shift registers in the essi are bidirectional. the msb/lsb selection is made by programming the shfd bit in the crb. if the shfd bit is cleared, data is shifted into the receive shift register msb first and shifted out of the transmit shift register msb first. if the shfd bit is set, data is shifted into the receive shift register lsb first and shifted out of the transmit shift register lsb first. 7.5.5 flags two essi signals (sc[1:0]) are available for use as serial i/o flags. their operation is controlled by the syn, scd[1:0], ssc1, and te[2:1] bits in the crb/cra.the control bits of[1:0] and status bits if[1:0] are double-buffered to/from sc[1:0]. double-buffering the flags keeps the flags in sync with tx and rx. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) gpio signals and registers motorola dsp56309um/d 7-43 the sc[1:0] flags are available in synchronous mode only. each flag can be separately programmed. flag sc0 is enabled when transmitter 1 is disabled (te1 = 0). the flag?s direction is selected by the scd0 bit. when scd0 is set, sc0 is configured as output. when scd0 is cleared, sc0 is configured as input. similarly, the sc1 flag is enabled when transmitter 2 is disabled (te2 = 0) and the sc1 signal is not configured as transmitter drive enable (bit ssc1 = 0). sc1?s direction is selected by the scd1 bit. when scd1 is set, sc1 is an output flag. when scd1 is cleared, sc1 is an input flag. when programmed as input flags, the value of the sc[1:0] bits are latched at the same time as the first bit of the receive data word is sampled. once the input has been latched, the signal on the input flag signal (sc0 and sc1) can change without affecting the input flag. the value of sc[1:0] does not change until the first bit of the next data word is received. when the received data word is latched by rx, the latched values of sc[1:0] are latched by the respective ssisr if[1:0] bits and can be read by software. when programed as output flags, the value of the sc[1:0] bits is taken from the value of the of[1:0] bits. the value of the of[1:0] bits is latched when the contents of tx are transferred to the transmit shift register. the value on sc[1:0] is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted. the of[1:0] values can be set directly by software. this allows the dsp56309 to control data transmission by indirectly controlling the value of the sc[1:0] flags. 7.6 gpio signals and registers the gpio functionality of an essi port (c, d) is controlled by three registers: port control register (pcrc, pcrd), port direction register (prrc, prrd) and port data register (pdrc, pdrd). 7.6.1 port control register (pcr) the read/write, 24-bit pcr controls the functionality of the essi gpio signals. each of pc[5:0] bits controls the functionality of the corresponding port signal. when a pc[i] bit is set, the corresponding port signal is configured as a essi signal. when a pc[i] bit is cleared, the corresponding port signal is configured as a gpio signal. either a hardware f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-44 dsp56309um/d motorola enhanced synchronous serial interface (essi) gpio signals and registers reset signal or a software reset instruction clears all pcr bits. figure 7-18 shows the pcr bits . 7.6.2 port direction register (prr) the read/write, 24-bit prr controls the data direction of the essi gpio signals. when prr[i] is set, the corresponding signal is an output signal. when prr[i] is cleared, the corresponding signal is an input signal. figure 7-19 shows the prr bits. figure 7-18 port control register (pcr) (pcrc x:$ffffbf) (pcrd x:$ffffaf) figure 7-19 port direction register (prr)(prrc x:$ffffbe) (prrd x:$ffffae) pc0 pc1 pc2 pc3 pc4 pc5 reserved bit, read as zero, should be written with zero for future compatibility 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 aa0688 stdn srdn sckn sckn2 sckn1 sckn0 pcrc: essi0, pcrd: essi1 0 = gpio, 1 = essi 0 1 2 3 4 5 6 7 pdc0 pdc1 pdc2 pdc3 pdc4 pdc5 reserved bit, read as zero, should be written with zero for future compatibility 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 aa0689 stdn srdn sckn sckn2 sckn1 sckn0 prrc: essi0, prrd: essi1 0 = input, 1 = output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . enhanced synchronous serial interface (essi) gpio signals and registers motorola dsp56309um/d 7-45 note: either a hardware reset signal or a software reset instruction clears all prr bits. table 7-5 shows the port signal configurations. 7.6.3 port data register (pdr) the read/write, 24-bit pdr is used to read or write data to and from the essi gpio signals. the pd[5:0] bits are used to read or write data from and to the corresponding port signals if they are configured as gpio signals. if a port signal [i] is configured as a gpio input, then the corresponding pd[i] bit reflects the value present on this signal. if a port signal [i] is configured as a gpio output, then the value written into the corresponding pd[i] bit is reflected on the this signal. figure 7-20 shows the pdr bits. table 7-5 port control register and port direction register bits pc[i] pdc[i] port signal[i] function 1 x essi 0 0 gpio input 0 1 gpio output note: x: the signal setting is irrelevant to port signal [i] function. figure 7-20 port data register (pdr) (pdrc x:$ffffbd) (pdrd x:$ffffad) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pd0 pd1 pd2 pd3 pd4 pd5 reserved bit, read as zero, should be written with zero for future compatibility 16 17 18 19 20 21 22 23 aa0690 stdn srdn sckn sckn2 sckn1 sckn0 pdrd: essi0, pdrd: essi1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7-46 dsp56309um/d motorola enhanced synchronous serial interface (essi) gpio signals and registers note: either a hardware reset signal or a software reset instruction clears all pdr bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 8-1 section 8 serial communication interface (sci) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-2 dsp56309um/d motorola serial communication interface (sci) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 sci i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 sci programming model . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.5 gpio signals and registers. . . . . . . . . . . . . . . . . . . 8-27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) introduction motorola dsp56309um/d 8-3 8.1 introduction the dsp56309 serial communication interface (sci) provides a full-duplex port for serial communication to other dsps, microprocessors, or peripherals such as modems. the sci interfaces without additional logic to peripherals that use ttl-level signals. with a small amount of additional logic, the sci can connect to peripheral interfaces that have non-ttl level signals, such as the rs232c, rs422, etc. this interface uses three dedicated signals: transmit data (txd), receive data (rxd), and sci serial clock (sclk). it supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission. the asynchronous protocols supported by the sci include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. this mode allows the dsp56309 to share a single serial line efficiently with other peripherals. the sci consists of separate transmit and receive sections that can operate asynchronously with respect to each other. a programmable baud-rate generator provides the transmit and receive clocks. an enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general purpose timer when it is not being used by the sci, or when the interrupt timing is the same as that used by the sci. 8.2 sci i/o signals each of the three sci signals (rxd, txd, and sclk) can be configured as either a gpio signal or as a specific sci signal. each signal is independent of the others. for example, if only the txd signal is needed, the rxd and sclk signals can be programmed for gpio. however, at least one of the three signals must be selected as an sci signal to release the sci from reset. sci interrupts can be enabled by programming the sci control registers before any of the sci signals are programmed as sci functions. in this case, only one transmit interrupt can be generated because the transmit data register is empty. the timer and timer interrupt operate regardless of how the sci pins are configured?either as sci or gpio. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-4 dsp56309um/d motorola serial communication interface (sci) sci programming model 8.2.1 receive data (rxd) this input signal receives byte-oriented serial data and transfers the data to the sci receive shift register. asynchronous input data is sampled on the positive edge of the receive clock (1 sclk) if sckp is cleared. rxd can be configured as a gpio signal (pe0) when the sci rxd function is not being used. 8.2.2 transmit data (txd) this output signal transmits serial data from the sci transmit shift register. data changes on the negative edge of the asynchronous transmit clock (sclk) if sckp is cleared. this output is stable on the positive edge of the transmit clock. txd can be programmed as a gpio signal (pe1) when the sci txd function is not being used. 8.2.3 sci serial clock (sclk) this bidirectional signal provides an input or output clock from which the transmit and/or receive baud rate is derived in asynchronous mode and from which data is transferred in synchronous mode. sclk can be programmed as a gpio signal (pe2) when the sci sclk function is not being used. this signal can be programmed as pe2 when data is being transmitted on txd, since the clock does not need to be transmitted in asynchronous mode. because sclk is independent of sci data i/o, there is no connection between programming the pe2 signal as sclk and data coming out the txd signal. 8.3 sci programming model the sci programming model can be viewed as three types of registers: control e sci control register (scr) in figure 8-1 e sci clock control register (sccr) in figure 8-3 status e sci status register (ssr) in figure 8-2 data transfer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-5 e sci receive data registers (srx) in figure 8-7 on page 8-19 e sci transmit data registers (stx) in figure 8-7 e sci transmit data address register (stxa) in figure 8-7 the sci also supports the gpio functions documented in section 8?gpio signals and registers on page 8-27. the following paragraphs describe each bit in the programming model. beginning on page 8-6, figure 8-4 shows the formats of data words. 76543210 woms rwu wake sbk ssftd wds2 wds1 wds0 15 14 13 12 11 10 9 8 sckp stir tmie tie rie ilie te re 23 22 21 20 19 18 17 16 reie aa0854 figure 8-1 sci control register (scr) 76543210 r8 fe pe or idle rdrf tdre trne 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 aa0855 figure 8-2 sci status register (ssr) 7 6 543210 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 15 14 13 12 11 10 9 8 tcm rcm scp cod cd11 cd10 cd9 cd8 23 22 21 20 19 18 17 16 reserved bit - read as 0 should be written with 0 for future compatibility aa0856 figure 8-3 sci clock control register (sccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-6 dsp56309um/d motorola serial communication interface (sci) sci programming model figure 8-4 sci data word formats mode 0 8-bit synchronous data (shift register mode) tx (ssftd = 0) one byte from shift register mode 2 10-bit asynchronous (1 start, 8 data, 1 stop) tx (ssftd = 0) d7 or data type stop bit mode 4 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) tx (ssftd = 0) d7 or data type stop bit even parity mode 5 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) tx (ssftd = 0) start bit d7 or data type stop bit odd parity mode 6 11-bit asynchronous multidrop (1 start, 8 data, 1 data type, 1 stop) tx (ssftd = 0) start bit stop bit data type note: 1. modes 1, 3, and 7 are reserved. 2. d0 = lsb; d7 = msb 3. data is transmitted and received lsb first if ssftd = 0, or msb first if ssftd = 1 d0 d1 d2 d3 d4 d5 d6 d7 010 d0 d1 d2 d3 d4 d5 d6 wds2 wds1 wds0 000 100 d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6 start bit wds2 wds1 wds0 start bit wds2 wds1 wds0 101 wds2 wds1 wds0 d0 d1 d2 d3 d4 d5 d6 d7 110 wds2 wds1 wds0 0 = data byte data type: 1 = address byte aa0691 ssftd = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-7 figure 8-4 sci data word formats (continued) mode 0 8-bit synchronous data (shift register mode) tx (ssftd = 1) one byte from shift register mode 2 10-bit asynchronous (1 start, 8 data, 1 stop) tx (ssftd = 1) start bit stop bit mode 4 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) tx (ssftd = 1) start bit stop bit even parity mode 5 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) tx (ssftd = 1) start bit d0 or data type stop bit odd parity mode 6 11-bit asynchronous multidrop (1 start, 8 data, 1 data type, 1 stop) tx (ssftd = 1) start bit stop bit data type d7 d6 d5 d4 d3 d2 d1 d0 wds2 wds1 wds0 000 note: 1. modes 1, 3, and 7 are reserved. 2. d0 = lsb; d7 = msb 3. data is transmitted and received lsb first if ssftd = 0, or msb first if ssftd = 1 0 = data byte data type: 1 = address byte aa0691 (cont.) d0 or data type d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 or data type d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 wds2 wds1 wds0 010 wds2 wds1 wds0 100 wds2 wds1 wds0 101 wds2 wds1 wds0 110 ssftd = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-8 dsp56309um/d motorola serial communication interface (sci) sci programming model 8.3.1 sci control register (scr) the scr is a 24-bit, read/write register that controls the serial interface operation. seventeen of the twenty-four bits are currently defined. each bit is described in the following paragraphs. 8.3.1.1 scr word select (wds[0:2]) bits 0e2 the word select wds[0:2] bits select the format of transmitted and received data. format modes are listed in table 8-1 below and shown in figure 8-4 on page 8-6. asynchronous modes are compatible with most uart-type serial devices and support standard rs232c communication links. multidrop asynchronous mode is compatible with the mc68681 duart, the m68hc11 sci interface, and the intel 8051 serial interface. synchronous data mode is essentially a high-speed shift register used for i/o expansion and stream-mode channel interfaces. a gated transmit and receive clock compatible with the intel 8051 serial interface mode 0 makes it possible for you to synchronize data. when odd parity is selected, the transmitter counts the number of 1s in the data word. if the total is not an odd number, the parity bit is set, thus producing an odd number. if the receiver counts an even number of 1s, an error in transmission has occurred. when even parity is selected, an even number must result from the calculation performed at both ends of the line, or an error in transmission has occurred. table 8-1 word formats wds2 wds1 wds0 mode word formats 0000 8-bit synchronous data (shift register mode) 0011 reserved 0102 10-bit asynchronous (1 start, 8 data, 1 stop) 0113 reserved 1004 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) 1015 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 1106 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) 1117 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-9 the word select bits are cleared by either a hardware reset signal or a software reset instruction. 8.3.1.2 scr sci shift direction (ssftd) bit 3 the ssftd bit determines the order in which the sci data shift registers shift data in or out: msb first when set, lsb first when cleared. the parity and data type bits do not change their position in the frame; they remain adjacent to the stop bit. ssftd is cleared by either a hardware reset signal or a software reset instruction. 8.3.1.3 scr send break (sbk) bit 4 a break is an all-zero word frame?a start bit 0, characters of all 0s (including any parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). if sbk is set and then cleared, the transmitter completes transmission of the current frame, sends ten or eleven 0s (depending on wds mode), and reverts to idle or sending data. if sbk remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with no stop bit). at the completion of the break code, the transmitter sends at least one high (set) bit before transmitting any data to guarantee recognition of a valid start bit. break can be used to signal an unusual condition, message, etc. by forcing a frame error, which is caused by a missing stop bit. either a hardware reset signal or a software reset instruction clears sbk. 8.3.1.4 scr wakeup mode select (wake) bit 5 when wake is cleared, the wakeup on idle line mode is selected. in the wakeup on idle line mode, the sci receiver is reenabled by an idle string of at least ten or eleven (depending on wds mode) consecutive 1s. the transmitter?s software must provide this idle string between consecutive messages. the idle string cannot occur within a valid message because each word frame contains a start bit that is 0. when wake is set, the wakeup on address bit mode is selected. in the wakeup on address bit mode, the sci receiver is reenabled when the last (eighth or ninth) data bit received in a character (frame) is 1. the ninth data bit is the address bit (r8) in the 11-bit multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asynchronous with parity modes. thus, the received character is an address that has to be processed by all sleeping processors?that is, each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. either a hardware reset signal or a software reset instruction clears wake. 8.3.1.5 scr receiver wakeup enable (rwu) bit 6 when rwu is set and the sci is in an asynchronous mode, the wakeup function is enabled?that is, the sci is asleep, and can be awakened by the event defined by the wake bit. in the sleep state, all interrupts and all receive flags except idle are disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-10 dsp56309um/d motorola serial communication interface (sci) sci programming model when the receiver wakes up, rwu is cleared by the wakeup hardware. the programmer can also clear the rwu bit to wake up the receiver. rwu can be used by the programmer to ignore messages that are for other devices on a multidrop serial network. wakeup on idle line (wake is cleared) or wakeup on address bit (wake is set) must be chosen. 1. when wake is cleared and rwu is set, the receiver does not respond to data on the data line until an idle line is detected. 2. when wake is set and rwu is set, the receiver does not respond to data on the data line until a data frame with the address bit set is detected. when the receiver wakes up, the rwu bit is cleared, and the first frame of data is received. if interrupts are enabled, the cpu is interrupted and the interrupt routine reads the message header to determine if the message is intended for this dsp. 1. if the message is for this dsp, the message is received, and rwu is set to wait for the next message. 2. if the message is not for this dsp, the dsp immediately sets rwu. setting rwu causes the dsp to ignore the remainder of the message and wait for the next message. either a hardware reset signal or a software reset instruction clears rwu. rwu is ignored in synchronous mode. 8.3.1.6 scr wired-or mode select (woms) bit 7 when the woms bit is set, the sci txd driver is programmed to function as an open-drain output and can be wired together with other txd signals in an appropriate bus configuration, such as a master-slave multidrop configuration. an external pullup resistor is required on the bus. when the woms is cleared, the txd signal uses an active internal pullup. either a hardware reset signal or a software reset instruction clears woms. 8.3.1.7 scr receiver enable (re) bit 8 when re is set, the receiver is enabled. when re is cleared, the receiver is disabled, and data transfer from the receive shift register to the receive data register (srx) is inhibited. if re is cleared while a character is being received, the reception of the character is completed before the receiver is disabled. re does not inhibit rdrf or receive interrupts. either a hardware reset signal or a software reset instruction clears re. 8.3.1.8 scr transmitter enable (te) bit 9 when te is set, the transmitter is enabled. when te is cleared, the transmitter completes transmission of data in the sci transmit data shift register, then the serial output is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-11 forced high (i.e., idle). data present in the sci transmit data register (stx) is not transmitted. stx can be written and tdre cleared, but the data is not transferred into the shift register. te does not inhibit tdre or transmit interrupts. either a hardware reset signal or a software reset instruction clears te. setting te causes the transmitter to send a preamble of ten or eleven consecutive 1s (depending on wds). this procedure gives the programmer a convenient way to insure that the line goes idle before starting a new message. to force this separation of messages by the minimum idle line time, the following sequence is recommended: 1. write the last byte of the first message to stx. 2. wait for tdre to go high, indicating the last byte has been transferred to the transmit shift register. 3. clear te and set te. this queues an idle line preamble to follow immediately the transmission of the last character of the message (including the stop bit). 4. write the first byte of the second message to stx. in this sequence, if the first byte of the second message is not transferred to stx prior to the finish of the preamble transmission, the transmit data line marks idle until stx is finally written. 8.3.1.9 scr idle line interrupt enable (ilie) bit 10 when ilie is set, the sci interrupt occurs when idle (sci status register bit 3) is set. when ilie is cleared, the idle interrupt is disabled. either a hardware reset signal or a software reset instruction clears ilie. an internal flag, the shift register idle interrupt (sriint) flag, is the interrupt request to the interrupt controller. sriint is not directly accessible to the user. when a valid start bit has been received, an idle interrupt is generated if both idle and ilie are set. the idle interrupt acknowledge from the interrupt controller clears this interrupt request. the idle interrupt is not asserted again until at least one character has been received. the results are as follows: 1. the idle bit shows the real status of the receive line at all times. 2. an idle interrupt is generated once for each idle state, no matter how long the idle state lasts. 8.3.1.10 scr sci receive interrupt enable (rie) bit 11 the rie bit is set to enable the sci receive data interrupt. if rie is cleared, the receive data interrupt is disabled, and then the rdrf bit in the sci status register must be f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-12 dsp56309um/d motorola serial communication interface (sci) sci programming model polled to determine if the receive data register is full. if both rie and rdrf are set, the sci requests an sci receive data interrupt from the interrupt controller. receive interrupts with exception have higher priority than normal receive data interrupts. therefore, if an exception occurs (i.e., if pe, fe, or or are set) and reie is set, the sci requests an sci receive data with exception interrupt from the interrupt controller. either a hardware reset signal or a software reset instruction clears rie. 8.3.1.11 scr sci transmit interrupt enable (tie) bit 12 the tie bit is set to enable the sci transmit data interrupt. if tie is cleared, transmit data interrupts are disabled, and the transmit data register empty (tdre) bit in the sci status register must be polled to determine if the transmit data register is empty. if both tie and tdre are set, the sci requests an sci transmit data interrupt from the interrupt controller. either a hardware reset signal or a software reset instruction clears tie. 8.3.1.12 scr timer interrupt enable (tmie) bit 13 the tmie bit is set to enable the sci timer interrupt. if tmie is set, timer interrupt requests are sent to the interrupt controller at the rate set by the sci clock register. the timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller. this feature allows dsp programmers to use the sci baud rate generator as a simple periodic interrupt generator if the sci is not in use, if external clocks are used for the sci, or if periodic interrupts are needed at the sci baud rate. the sci internal clock is divided by 16 (to match the 1 sci baud rate) for timer interrupt generation. this timer does not require that any sci signals be configured for sci use to operate. either a hardware reset signal or a software reset instruction clears tmie. 8.3.1.13 scr timer interrupt rate (stir) bit 14 the stir bit controls a divide-by-32 in the sci timer interrupt generator. when stir is cleared, the divide-by-32 is inserted in the chain. when stir is set, the divide-by-32 is bypassed, thereby increasing timer resolution by a factor of 32. either a hardware reset signal or a software reset instruction clears this bit. to insure proper operation of the timer, stir must not be changed during timer operation (i.e., if tmie = 1). 8.3.1.14 scr sci clock polarity (sckp) bit 15 the sckp bit controls the clock polarity sourced or received on the clock signal (sclk), eliminating the need for an external inverter. when sckp is cleared, the clock polarity is positive. when sckp is set, the clock polarity is negative. in synchronous mode, positive polarity means that the clock is normally positive and transitions negative during valid data. negative polarity means that the clock is normally negative and transitions positive during valid data. in asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid. negative polarity means that the falling edge of the clock occurs during the center of the period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-13 that data is valid. either a hardware reset signal or a software reset instruction clears sckp. 8.3.1.15 receive with exception interrupt enable (reie) bit 16 the reie bit is set to enable the sci receive data with exception interrupt. if reie is cleared, the receive data with exception interrupt is disabled. if both reie and rdrf are set, and pe, fe, and or are not all cleared, the sci requests an sci receive data with exception interrupt from the interrupt controller. either a hardware reset signal or a software reset instruction clears reie. 8.3.2 sci status register (ssr) the ssr is a 24-bit, read-only register used by the dsp to determine the status of the sci. the status bits are described in the following paragraphs. 8.3.2.1 ssr transmitter empty (trne) bit 0 the trne flag bit is set when both the transmit shift register and transmit data register (stx) are empty to indicate that there is no data in the transmitter. when trne is set, data written to one of the three stx locations or to the transmit data address register (stxa) is transferred to the transmit shift register and is the first data transmitted. trne is cleared when tdre is cleared by writing data into the stx or the stxa, or when an idle, preamble, or break is transmitted. this bit, when set, indicates that the transmitter is empty; therefore, the data written to stx or stxa is transmitted next. that is, there is no word in the transmit shift register presently being transmitted. this procedure is useful when initiating the transfer of a message (i.e., a string of characters). trne is set by a hardware reset signal, software reset instruction, sci individual reset, or stop instruction. 8.3.2.2 ssr transmit data register empty (tdre) bit 1 the tdre flag bit is set when the sci transmit data register is empty. when tdre is set, new data can be written to one of the sci transmit data registers (stx) or the transmit data address register (stxa). tdre is cleared when the sci transmit data register is written. tdre is set by the hardware reset signal, software reset instruction, sci individual reset, or stop instruction. in synchronous mode, when using the internal sci clock, there is a delay of up to 5.5 serial clock cycles between the time that stx is written until tdre is set, indicating the data has been transferred from the stx to the transmit shift register. there is a 2 to 4 serial clock cycle delay between writing stx and loading the transmit shift register; in addition, tdre is set in the middle of transmitting the second bit. when using an external serial transmit clock, if the clock stops, the sci transmitter stops. tdre is not set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-14 dsp56309um/d motorola serial communication interface (sci) sci programming model until the middle of the second bit transmitted after the external clock starts. gating the external clock off after the first bit has been transmitted delays tdre indefinitely. in asynchronous mode, the tdre flag is not set immediately after a word is transferred from the stx or stxa to the transmit shift register nor when the word first begins to be shifted out. tdre is set two cycles of the 16 clock after the start bit? that is, two 16 clock cycles into the transmission time of the first data bit. 8.3.2.3 ssr receive data register full (rdrf) bit 2 the rdrf bit is set when a valid character is transferred to the sci receive data register from the sci receive shift register (regardless of the error bits condition). rdrf is cleared when the sci receive data register is read or by a hardware reset signal, software reset instruction, sci individual reset, or stop instruction. 8.3.2.4 ssr idle line flag (idle) bit 3 idle is set when 10 (or 11) consecutive 1s are received. idle is cleared by a start-bit detection. the idle status bit represents the status of the receive line. the transition of idle from 0 to 1 can cause an idle interrupt (ilie). idle is cleared by a hardware reset signal, software reset instruction, sci individual reset, or stop instruction. 8.3.2.5 ssr overrun error flag (or) bit 4 the or flag bit is set when a byte is ready to be transferred from the receive shift register to the receive data register (srx) that is already full (rdrf = 1). the receive shift register data is not transferred to the srx. the or flag indicates that character(s) in the received data stream may have been lost. the only valid data is located in the srx. or is cleared when the sci status register is read, followed by a read of srx. the or bit clears the fe and pe bits?that is, an overrun error has higher priority than fe or pe. or is cleared by a hardware reset signal, software reset instruction, sci individual reset, or stop instruction. 8.3.2.6 ssr parity error (pe) bit 5 in the 11-bit asynchronous modes, the pe bit is set when an incorrect parity bit has been detected in the received character. it is set simultaneously with rdrf for the byte which contains the parity error?that is, when the received word is transferred to the srx. if pe is set, further data transfer into the srx is not inhibited. pe is cleared when the sci status register is read, followed by a read of srx. pe is also cleared by a hardware reset signal, software reset instruction, sci individual reset, or stop instruction. in 10-bit asynchronous mode, 11-bit multidrop mode, and 8-bit synchronous mode, the pe bit is always cleared since there is no parity bit in these modes. if the byte received causes both parity and overrun errors, the sci receiver recognizes only the overrun error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-15 8.3.2.7 ssr framing error flag (fe) bit 6 the fe bit is set in asynchronous modes when no stop bit is detected in the data string received. fe and rdre are set simultaneously when the received word is transferred to the srx. however, the fe flag inhibits further transfer of data into the srx until it is cleared. fe is cleared when the sci status register is read followed by reading the srx. a hardware reset signal, software reset instruction, sci individual reset, or stop instruction also clears fe. in 8-bit synchronous mode, fe is always cleared. if the byte received causes both framing and overrun errors, the sci receiver recognizes only the overrun error. 8.3.2.8 ssr received bit 8 (r8) address bit 7 in 11-bit asynchronous multidrop mode, the r8 bit is used to indicate whether the received byte is an address or data. r8 is set for addresses and is cleared for data. r8 is not affected by reading the srx or sci status register. a hardware reset signal, software reset instruction, sci individual reset, or stop instruction also clears r8. 8.3.3 sci clock control register (sccr) the sccr is a 24-bit, read/write register that controls the selection of the clock modes and baud rates for the transmit and receive sections of the sci interface. the control bits are described in the following paragraphs. the sccr is cleared by a hardware reset signal. the basic features of the clock generator (as in figure 8-5 on page 8-16 and figure 8-6 on page 8-18) are these: the sci logic always uses a 16 internal clock in asynchronous modes and always uses a 2 internal clock in synchronous mode. the maximum internal clock available to the sci peripheral block is the oscillator frequency divided by 4. the 16 clock is necessary for asynchronous modes to synchronize the sci to the incoming data, as in figure 8-5 . for asynchronous modes, the user must provide a 16 clock to use an external baud rate generator (i.e., sclk input). for asynchronous modes, the user can select either 1 or 16 for the output clock when using internal tx and rx clocks (tcm = 0 and rcm = 0). when sckp is cleared, the transmitted data on the txd signal changes on the negative edge of the 1 serial clock and is stable on the positive edge. when sckp is set, the data changes on the positive edge and is stable on the negative edge. the received data on the rxd signal is sampled on the positive edge (if sckp = 0) or on the negative edge (if sckp = 1) of the 1 serial clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-16 dsp56309um/d motorola serial communication interface (sci) sci programming model for asynchronous mode, the output clock is continuous. for synchronous mode, a 1 clock is used for the output or input baud rate. the maximum 1 clock is the crystal frequency divided by 8. for synchronous mode, the clock is gated. for synchronous mode, the transmitter and receiver are synchronous with each other. 8.3.3.1 sccr clock divider (cd[11:0]) bits 11e0 the cd[11:0] bits specify the divide ratio of the prescale divider in the sci clock generator. a divide ratio from 1 to 4096 (cd[11:0] = $000 to $fff) can be selected. either a hardware reset signal or a software reset instruction clears cd11ecd0. 8.3.3.2 sccr clock out divider (cod) bit 12 the clock output divider is controlled by cod and sci mode. if sci mode is synchronous, the output divider is fixed at divide by 2. if sci mode is asynchronous, then one of the following conditions occurs: if cod is cleared and sclk is an output (i.e., tcm and rcm are both cleared), the sci clock is divided by 16 before being output to the sclk signal. thus, the sclk output is a 1 clock. if cod is set and sclk is an output, the sci clock is fed directly out to the sclk signal. thus, the sclk output is a 16 baud clock. either a hardware reset signal or a software reset instruction clears cod. figure 8-5 16 x serial clock rx, tx data (ssftd = 0) idle line start select 8-or 9-bit words x1 clock x16 clock (sckp = 0) 1 0 2345678 aa0692 stop start f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-17 8.3.3.3 sccr sci clock prescaler (scp) bit 13 the scp bit selects a divide by 1 (scp is cleared) or divide by 8 (scp is set) prescaler for the clock divider. the output of the prescaler is further divided by 2 to form the sci clock. either a hardware reset signal or a software reset instruction clears scp. 8.3.3.4 sccr receive clock mode source (rcm) bit 14 rcm selects whether an internal or external clock is used for the receiver. if rcm is cleared, the internal clock is used. if rcm is set, the external clock (from the sclk signal) is used. either a hardware reset signal or a software reset instruction clears rcm. table 8-2 tcm and rcm bit configuration tcm rcm tx clock rx clock sclk signal mode 0 0 internal internal output synchronous/asynchronous 0 1 internal external input asynchronous only 1 0 external internal input asynchronous only 1 1 external external input synchronous/asynchronous f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-18 dsp56309um/d motorola serial communication interface (sci) sci programming model 8.3.3.5 sccr transmit clock source bit (tcm) bit 15 tcm selects whether an internal or external clock is used for the transmitter. if tcm is cleared, the internal clock is used. if tcm is set, the external clock (from the sclk signal) is used. either a hardware reset signal or a software reset instruction clears tcm. 8.3.4 sci data registers the sci data registers are divided into two groups: receive and transmit (as in figure 8-7 ). there are two receive registers?a receive data register (srx) and a serial-to-parallel receive shift register. there are also two transmit registers?a transmit data register (called either stx or stxa) and a parallel-to-serial transmit shift register. figure 8-6 sci baud rate generator f core divide by 2 12-bit counter prescaler: divide by 1 or 8 cd11ecd0 scp internal clock timer interrupt (stmint) sci core logic uses divide by 16 for asynchronous uses divide by 2 for synchronous cod sckp if asynchronous divide by 1 or 16 if synchronous divide by 2 to sclk f core bps = 64 ((7 scp + 1) cd + 1) where: scp = 0 or 1 cd = $000 to $fff aa0693 divide by 2 divide by 16 sckp = 0 sckp = 1 + e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) sci programming model motorola dsp56309um/d 8-19 8.3.4.1 sci receive registers (srx) data bits received on the rxd signal are shifted into the sci receive shift register. when a complete word has been received, the data portion of the word is transferred to the byte-wide srx. this process converts the serial data to parallel data and provides double-buffering. double-buffering provides flexibility to the programmer and increased throughput since the programmer can save (and process) the previous word while the current word is being received. the srx can be read at three locations as srxl, srxm, and srxh. when srxl is read, the contents of the srx are placed in the lower byte of the data bus and the remaining bits on the data bus are read as 0s. similarly, when srxm is read, the contents of srx are placed in the middle byte of the bus, and when srxh is read, the contents of srx are placed in the high byte with the remaining bits read as 0s. mapping srx as described allows three bytes to be efficiently packed into one 24-bit word by oring three data bytes read from the three addresses. figure 8-7 sci programming model data registers srx srx srx rxd sci receive data shift register note: 1. srx is the same register decoded at three different addresses. stx stx stx txd sci transmit data shift register note: 1. bytes are masked on the fly. 2. stx is the same register decoded at four different addresses. stxa (a) receive data register (b) transmit data register aa0694 sci receive data register high (read only) sci receive data register middle (read only) sci receive data register low (read only) 0 7 8 15 16 23 0 7 8 15 16 23 0 7 8 15 16 23 sci transmit data register high (write only) sci transmit data register middle (write only) sci transmit data register low (write only) sci transmit data address register (write only) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-20 dsp56309um/d motorola serial communication interface (sci) sci programming model the length and format of the serial word are defined by the wds0, wds1, and wds2 control bits in the scr. the clock source is defined by the receive clock mode (rcm) select bit in the scr. in synchronous mode, the start bit, the eight data bits, the address/data indicator bit and/or the parity bit, and the stop bit are received in that order. data bits are sent lsb first if ssftd is cleared, and msb first if ssftd is set. in synchronous mode, the synchronization is provided by gating the clock. in either synchronous or asynchronous mode, when a complete word has been clocked in, the contents of the shift register can be transferred to the srx and the flags; rdrf, fe, pe, and or are changed appropriately. because the operation of the receive shift register is transparent to the dsp, the contents of this register are not directly accessible to the programmer. 8.3.4.2 sci transmit registers the transmit data register is a one byte-wide register mapped into four addresses as stxl, stxm, stxh, and stxa. in asynchronous mode, when data is to be transmitted, stxl, stxm, and stxh are used. when stxl is written, the low byte on the data bus is transferred to the stx. when stxm is written, the middle byte is transferred to the stx. when stxh is written, the high byte is transferred to the stx. this structure makes it easy for the programmer to unpack the bytes in a 24-bit word for transmission. tdxa should be written in the 11-bit asynchronous multidrop mode when the data is an address and it is desired that the ninth bit (the address bit) be set. when stxa is written, the data from the low byte on the data bus is stored in it. the address data bit is cleared in the 11-bit asynchronous multidrop mode when any of stxl, stxm or stxh is written. when either stx (stxl, stxm, or stxh) or stxa is written, tdre is cleared. the transfer from either stx or stxa to the transmit shift register occurs automatically, but not immediately, when the last bit from the previous word has been shifted out; that is, the transmit shift register is empty. like the receiver, the transmitter is double-buffered. however, a 2 to 4 serial clock cycle delay occurs between when the data is transferred from either stx or stxa to the transmit shift register and when the first bit appears on the txd signal. (a serial clock cycle is the time required to transmit one data bit). the transmit shift register is not directly addressable, and a dedicated flag for this register does not exist. because of this fact and the 2 to 4 cycle delay, two bytes cannot be written consecutively to stx or stxa without polling, as the second byte might overwrite the first byte. the tdre flag should always be polled prior to writing stx or stxa to prevent overruns unless transmit interrupts have been enabled. either stx or stxa is usually written as part of the interrupt service routine. an interrupt is generated only if tdre is set. the transmit shift register is indirectly visible via the trne bit in the ssr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) operating modes motorola dsp56309um/d 8-21 in synchronous mode, data is synchronized with the transmit clock, which can have either an internal or external source, as defined by the tcm bit in the sccr. the length and format of the serial word is defined by the wds0, wds1, and wds2 control bits in the scr. in asynchronous modes, the start bit, the eight data bits (with the lsb first if ssftd = 0 and the msb first if ssftd = 1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order. the data to be transmitted can be written to any one of the three stx addresses. if sckp is set and sshtd is set, the sci synchronous mode is equivalent to the ssi operation in the 8-bit data on-demand mode. note: when writing data to a peripheral device, there is a two cycle pipeline delay until any status bits affected by this operation are updated. if you read any of those status bits within the next two cycles, the bit does not reflect its current status. see the dsp56300 family manual, appendix b, polling a peripheral device for write for further details. 8.4 operating modes the operating modes for the dsp56309 sci are these: 8-bit synchronous (shift register mode) 10-bit asynchronous (1 start, 8 data, 1 stop) 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop) this mode is used for master/slave operation with wakeup on idle line and wakeup on address bit capability. it allows the dsp56309 to share a single serial line efficiently with other peripherals. these modes are selected using the wd[0:2] bits in the scr. the synchronous data mode is essentially a high-speed shift register used for i/o expansion and stream-mode channel interfaces. data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the intel 8051 serial interface mode 0. asynchronous modes are compatible with most uart-type serial devices. standard rs232c communication links are supported by these modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-22 dsp56309um/d motorola serial communication interface (sci) operating modes the multidrop asynchronous modes are compatible with the mc68681 duart, the m68hc11 sci interface, and the intel 8051 serial interface. 8.4.1 sci after reset there are four different methods of resetting the sci. 1. hardware reset signal 2. software reset instruction: both hardware and software resets clear the port control register bits, which configure all i/o as gpio input. the sci remains in the reset state as long as all sci signals are programmed as gpio (pc2, pc1, and pc0 all are cleared); the sci becomes active only when at least one of the sci i/o signals is not programmed as gpio. 3. individual reset: during program execution, the pc2, pc1, and pc0 bits can be cleared (individual reset), which causes the sci to stop serial activity and enter the reset state. all sci status bits are set to their reset state. however, the contents of the scr are not affected, allowing the dsp program to reset the sci separately from the other internal peripherals. during individual reset, internal dma accesses to the data registers of the sci are not valid and the data read is unknown. 4. stop processing state reset: executing the stop instruction halts operation of the sci until the dsp is restarted, causing the ssr to be reset. no other sci registers are affected by the stop instruction. table 8-3 on page 8-23 illustrates how each type of reset affects each register in the sci. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) operating modes motorola dsp56309um/d 8-23 table 8-3 sci registers after reset register bit bit mnemonic bit number reset type hw reset sw reset ir reset st reset reie 16 0 0 ? ? sckp 15 0 0 ? ? stir 14 0 0 ? ? tmie 13 0 0 ? ? tie 12 0 0 ? ? rie 11 0 0 ? ? ilie 10 0 0 ? ? te 9 0 0 ? ? scr re 8 0 0 ? ? woms 7 0 0 ? ? rwu 6 0 0 ? ? wake 5 0 0 ? ? sbk 4 0 0 ? ? ssftd 3 0 0 ? ? wds[2:0] 2e0 0 0 ? ? r8 7 0 0 0 0 fe 6 0 0 0 0 pe 5 0 0 0 0 ssr or 4 0 0 0 0 idle 3 0 0 0 0 rdrf 2 0 0 0 0 tdre 1 1 1 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-24 dsp56309um/d motorola serial communication interface (sci) operating modes 8.4.2 sci initialization the correct way to initialize the sci is as follows: 1. send a hardware reset signal or software reset instruction. 2. program sci control registers. 3. configure at least one sci signal as other than gpio. trne 0 1 1 1 1 tcm 15 0 0 ? ? rcm 14 0 0 ? ? sccr scp 13 0 0 ? ? cod 12 0 0 ? ? cd[11:0] 11e0 0 0 ? ? srx srx [23:0] 23e16, 15e8, 7e0 ? ? ? ? stx stx[23:0] 23e0 ? ? ? ? srsh srs[8:0] 8e0 ? ? ? ? stsh sts[8:0] 8e0 ? ? ? e note: srsh?sci receive shift register, stsh ? sci transmit shift register hw?hardware reset is caused by asserting the external reset signal. sw?software reset is caused by executing the reset instruction. ir?individual reset is caused by clearing pcre (bits 0e2) (configured for gpio ). st?stop reset is caused by executing the stop instruction. 1?the bit is set during this reset. 0?the bit is cleared during this reset. ? ? the bit is not changed during this reset table 8-3 sci registers after reset (continued) register bit bit mnemonic bit number reset type hw reset sw reset ir reset st reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) operating modes motorola dsp56309um/d 8-25 if interrupts are to be used, the signals must be selected, and interrupts must be enabled and unmasked before the sci can operate. the order does not matter; any one of these three requirements for interrupts can be used to enable the sci. synchronous applications usually require exact frequencies, which require that the crystal frequency be chosen carefully. an alternative to selecting the system clock to accommodate the sci requirements is to provide an external clock to the sci. 8.4.3 sci initialization example one way to initialize the sci is described here as an example. 1. the sci should be in its individual reset state (pcr = $0). 2. configure the control registers (scr, sccr) according to the operating mode, but do not enable either transmitter (te = 0) or receiver (re = 0). it is possible to set the interrupt enable bits that would be in use during the operation (no interrupt occurs). 3. enable the sci by setting the pcr bits according to which signals will be in use during operation. 4. if transmit interrupt is not used, write data to the transmitter. if transmitter interrupt enable is set, an interrupt is issued and the interrupt handler should write data into the transmitter. sci transmit request is serviced by dma channel if it is programmed to service the sci transmitter. 5. enable transmitters (te = 1) and receiver (re = 1), according to usage. operation starts as follows: for an internally generated clock, the sclk signal starts operation immediately after the sci is enabled (step 3 above) for asynchronous modes. in synchronous mode, the sclk signal is active only while transmitting (gated clock). data is received only when the receiver is enabled (re = 1) and after the occurrence of the sci receive sequence on the rxd signal, as defined by the operating mode (i.e., idle line sequence). data is transmitted only after the transmitter is enabled (te = 1), and after transmitting the initialization sequence depending on the operating mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-26 dsp56309um/d motorola serial communication interface (sci) operating modes 8.4.4 preamble, break, and data transmission priority two or three transmission commands can be set simultaneously: 1. a preamble (te is set.) 2. a break (sbk is set or is cleared.) 3. there is data for transmission (tdre is cleared.) after the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order: 1. preamble 2. break 3. data 8.4.5 sci exceptions the sci can cause five different exceptions in the dsp. these exceptions are as follows (ordered from the highest to the lowest priority): 1. sci receive data with exception status is caused by receive data register full with a receiver error (parity, framing, or overrun error). clearing the pending interrupt is done by reading the sci status register, followed by a read of srx. a long interrupt service routine should be used to handle the error condition. this interrupt is enabled by scr bit 16 (reie). 2. sci receive data is caused by receive data register full. reading srx clears the pending interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead. this interrupt is enabled by scr bit 11 (rie). 3. sci transmit data is caused by transmit data register empty. writing stx clears the pending interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead. this interrupt is enabled by scr bit 12 (tie). 4. sci idle line is caused by the receive line entering the idle state (10 or 11 bits of 1s). this interrupt is latched and then automatically reset when the interrupt is accepted. this interrupt is enabled by scr bit 10 (ilie). 5. sci timer is caused by the baud rate counter reaching zero. this interrupt is automatically reset when the interrupt is accepted. this interrupt is enabled by scr bit 13 (tmie). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) gpio signals and registers motorola dsp56309um/d 8-27 8.5 gpio signals and registers the gpio functionality of port sci is controlled by three registers: port e control register (pcre), port e direction register (prre) and port e data register (pdre). 8.5.1 port e control register (pcre) the read/write, 24-bit pcre controls the functionality of sci gpio signals. each of the pc[2:0] bits controls the functionality of the corresponding port signal. when a pc[i] bit is set, the corresponding port signal is configured as a sci signal. when a pc[i] bit is cleared, the corresponding port signal is configured as a gpio signal. bits in the port e control register appear in figure 8-8 . note: a hardware reset signal or a software reset instruction clears all pcr bits. 8.5.2 port e direction register (prre) the read/write, 24-bit prre controls the direction of sci gpio signals. when port signal[i] is configured as gpio, pdc[i] controls the port signal direction. when pdc[i] is set, the gpio port signal[i] is configured as output. when pdc[i] is cleared, the gpio port signal[i] is configured as input. bits in the port e direction register appear in figure 8-9 . figure 8-8 port e control register (pcre) pc0 pc1 pc2 reserved bit, read as 0, should be written with 0 for future compatibility port control bits: 1 = sci 0 = gpio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 aa0695 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-28 dsp56309um/d motorola serial communication interface (sci) gpio signals and registers note: a hardware reset signal or a software reset instruction clears all prr bits. table 8-4 shows the port signal configurations. 8.5.3 port e data register (pdre) the read/write, 24-bit pdre is used to read or write data to or from sci gpio signals. bits pd[2:0] are used to read or write data from or to the corresponding port signals if they are configured as gpio. if a port signal[i] is configured as a gpio input, then the corresponding pd[i] bit reflects the value of this signal. if a port signal[i] is configured as a gpio output, then the value of the corresponding pd[i] bit is reflected on this signal. bits of the port e data register appear in figure 8-10 . figure 8-9 port e direction register (prre) table 8-4 port control register and port direction register bits pc[i] pdc[i] port signal[i] function 1 1 or 0 sci 0 0 gpio input 0 1 gpio output 0 1 2 3 4 5 6 7 pdc0 pdc1 pdc2 direction control bits: 1 = output 0 = input 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 reserved bit, read as 0, should be written with 0 for future compatibility aa0696 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) gpio signals and registers motorola dsp56309um/d 8-29 note: a hardware reset signal or a software reset instruction clears all pdre bits. figure 8-10 port e data register (pdre) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pd0 pd1 pd2 16 17 18 19 20 21 22 23 reserved bit, read as 0, should be written with 0 for future compatibility aa0697 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8-30 dsp56309um/d motorola serial communication interface (sci) gpio signals and registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 9-1 section 9 triple timer module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-2 dsp56309um/d motorola triple timer module 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 triple timer module architecture . . . . . . . . . . . . 9-3 9.3 triple timer module programming model. . . . . . 9-5 9.4 timer operational modes. . . . . . . . . . . . . . . . . . . . . 9-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module introduction motorola dsp56309um/d 9-3 9.1 introduction this section describes the internal triple timer module in the dsp56309. each timer has a single signal that can be used as a gpio signal or as a timer signal. these three timers can be used to generate timed pulses or as pulse width modulators. they can also be used as an event counter, to capture an event, or to measure the width or period of a signal. 9.2 triple timer module architecture the timer module is composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each having its own register set. each timer can use internal or external clocking and can interrupt the dsp56309 after a specified number of events (clocks) or can signal an external device after counting internal events. each timer can also be used to trigger dma transfers after a specified number of events (clocks) has occurred. each timer connects to the external world through one bidirectional signal, designated tio0etio2 for timers 0e2, respectively. when the tio signal is configured as input, the timer functions as an external event counter or measures external pulse width/signal period. when the tio signal is used as output, the timer functions as a timer, a watchdog timer, or a pulse width modulator. when the tio signal is not used by the timer, it can be used as a gpio signal (also called tio0etio2). 9.2.1 triple timer module block diagram figure 9-1 shows a block diagram of the triple timer module. this module includes a 24-bit timer prescaler load register (tplr), a 24-bit timer prescaler count register (tpcr), a 21-bit prescaler clock counter, and three timers. each of the three timers can use the prescaler clock as its clock source. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-4 dsp56309um/d motorola triple timer module triple timer module architecture 9.2.2 timer block diagram the timer block diagram (in figure 9-2 ) shows the structure of a timer module. the timer programmer?s model (in figure 9-3 on page 9-6) shows the structure of the timer registers. the three timers are identical in structure and function. a generic timer is discussed in this section. the timer includes a 24-bit counter, a 24-bit read/write timer control and status register (tcsr), a 24-bit read-only timer count register (tcr), a 24-bit write-only timer load register (tlr), a 24-bit read/write timer compare register (tcpr), and logic for clock selection and interrupt/dma trigger generation. the timer mode is controlled by the tc[3:0] bits of the timer control/status register (tcsr). for a listing of the timer modes, see section 9?timer operational modes . for a description of their operation, see section 9.4.1?timing modes . figure 9-1 triple timer module block diagram timer prescaler count register gdb 24 24 tplr 24 timer 0 timer 2 timer 1 21-bit counter clk/2 tio0 tio1 tio2 tpcr timer prescaler load register 24 aa0673 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-5 the dsp56309 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the x data memory space. either standard polled or interrupt programming techniques can be used to service the timers. the timer programming model is shown in figure 9-3 on page 9-6. 9.3 triple timer module programming model the programming model for the triple timer module appears in figure 9-3 on page 9-6. figure 9-2 timer module block diagram gdb control/status register tcsr counter timer interrupt/ timer control clk/2 tio compare register tcpr = 24 24 dma request logic load register count register tlr prescaler clk tcr aa0676 24 24 9 2 24 24 24 24 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-6 dsp56309um/d motorola triple timer module triple timer module programming model figure 9-3 timer module programmer?s model do di dir 15 14 13 12 11 10 9 8 tc1 tc0 inv tcie te 76543210 timer control/status register (tcsr) - reserved, read as 0, should be written with 0 for future compatibility 23 0 timer load register (tlr) 23 22 21 20 19 18 17 16 23 0 timer compare register (tcpr) pce trm tcf tof toie tc2 23 0 timer count register (tcr) tc3 tcsr0 = $ffff8f tcsr1 = $ffff8b tcsr2 = $ffff87 tlr0 = $ffff8e tlr1 = $ffff8a tlr2 = $ffff86 tcr0 = $ffff8c tcr1 = $ffff88 tcr2 = $ffff84 tcpr0 = $ffff8d tcpr1 = $ffff89 tcpr2 = $ffff85 23 0 timer prescaler load register (tplr) tplr = $ffff83 23 0 timer prescaler count register (tpcr) tplr = $ffff82 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-7 9.3.1 prescaler counter the prescaler counter is a 21-bit counter that is decremented on the rising edge of the prescaler input clock. the counter is enabled when at least one of the three timers is enabled (i.e., one or more of the timer enable (te) bits are set) and is using the prescaler output as its source (i.e., one or more of the pce bits are set). 9.3.2 timer prescaler load register (tplr) the tplr is a 24-bit, read/write register that controls the prescaler divide factor (i. e., the number that the prescaler counter loads and begins counting from) and the source for the prescaler input clock. the control bits are shown below in figure 9-4 . 9.3.2.1 tplr prescaler preload value (pl[20:0]) bits 20-0 these 21 bits contain the prescaler preload value. this value is loaded into the prescaler counter when the counter value reaches 0, or the counter switches state from disabled to enabled. if pl[20:0] = n, then the prescaler counts n + 1 source clock cycles before generating a prescaler clock pulse. therefore, the prescaler divide factor = (preload value) + 1. the pl[20:0] bits are cleared by a hardware reset signal or a software reset instruction. 9.3.2.2 tplr prescaler source (ps[1:0]) bits 22-21 the two ps bits control the source of the prescaler clock. table 9-1 summarizes ps bit functionality. the prescaler?s use of a tio signal is not affected by the tcsr settings of the timer corresponding to the tio signal being used. 23 22 21 20 19 18 17 16 15 14 13 12 ps1 ps0 pl20 pl19 pl18 pl17 pl16 pl15 pl14 pl13 pl12 11109876543210 pl11 pl10 pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 ? reserved, read as 0, should be written with 0 for future compatibility figure 9-4 timer prescaler load register (tplr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-8 dsp56309um/d motorola triple timer module triple timer module programming model if the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the tio signal. the external clock is internally synchronized to the internal clock. the external clock frequency must be lower than the dsp56309 internal operating frequency divided by 4 (clk/4). the ps[1:0] bits are cleared by a hardware reset signal or a software reset instruction. note: to insure proper operation, change the ps[1:0] bits only when the prescaler counter is disabled. disable the prescaler counter by clearing the te bit in the tcsr of each of three timers. 9.3.2.3 tplr reserved bit 23 this reserved bit is read as 0 and should be written with 0 for future compatibility. 9.3.3 timer prescaler count register (tpcr) the tpcr is a 24-bit, read-only register that reflects the current value in the prescaler counter. the register bits are shown in figure 9-5 . table 9-1 prescaler source selection ps1 ps0 prescaler clock source 0 0 internal clk/2 0 1 tio0 1 0 tio1 1 1 tio2 23 22 21 20 19 18 17 16 15 14 13 12 pc20 pc19 pc18 pc17 pc16 pc15 pc14 pc13 pc12 11109876543210 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ? reserved, read as 0, should be written with 0 for future compatibility figure 9-5 timer prescaler count register (tpcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-9 9.3.3.1 tpcr prescaler counter value (pc[20:0]) bits 20-0 these 21 bits contain the current value of the prescaler counter. 9.3.3.2 tpcr reserved bits 23-21 these reserved bits are read as 0 and should be written with 0 for future compatibility. 9.3.4 timer control/status register (tcsr) the tcsr is a 24-bit, read/write register controlling the timer and reflecting its status. the register bits are shown in figure 9-6 . the control and status bits are documented in table 9-2 on page 9-10. 9.3.4.1 timer enable (te) bit 0 the te bit is used to enable or disable the timer. setting te enables the timer and clears the timer counter. the counter starts counting according to the mode selected by the timer control (tc[3:0]) bit values. clearing the te bit disables the timer. the te bit is cleared by a hardware reset signal or a software reset instruction. note: when all three timers are disabled and the signals are not in gpio mode, all three tio signals are tri-stated. to prevent undesired spikes on the tio signals when switching from tri-state into active state, these signals should be tied to the high or low signal state by the use of pull-up or pull-down resistors. 9.3.4.2 timer overflow interrupt enable (toie) bit 1 the toie bit is used to enable the timer overflow interrupts. setting toie enables overflow interrupt generation. the timer counter can hold a maximum value of $ffffff. when the counter value is at the maximum value and a new event causes the counter to be incremented to $000000, the timer generates an overflow interrupt. 23 22 21 20 19 18 17 16 15 14 13 12 tcf tof pce do di 11109876543210 dir trm inv tc3 tc2 tc1 tc0 tcie toie te ? reserved, read as 0, should be written with 0 for future compatibility figure 9-6 timer control/status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-10 dsp56309um/d motorola triple timer module triple timer module programming model clearing the toie bit disables overflow interrupt generation. the toie bit is cleared by a hardware reset signal or a software reset instruction. 9.3.4.3 timer compare interrupt enable (tcie) bit 2 the tcie bit is used to enable or disable the timer compare interrupts. setting tcie enables the compare interrupts. in the timer, pulse width modulation (pwm), or watchdog modes, a compare interrupt is generated after the counter value matches the value of the tcpr. the counter starts counting up from the number loaded from the tlr and if the tcpr value is n, an interrupt occurs after (n e m + 1) events, where m is the value of tlr. clearing the tcie bit disables the compare interrupts. the tcie bit is cleared by a hardware reset signal or a software reset instruction. 9.3.4.4 timer control (tc[3:0]) bits 4-7 the four tc bits control the source of the timer clock, the behavior of the tio signal, and timer mode. table 9-2 summarizes the tc bit functionality. there is a detailed description of the timer operating modes in section 9.4?timer operational modes . the tc bits are cleared by a hardware reset signal or a software reset instruction. note: if the clock is external, the counter is incremented by the transitions on the tio signal. the external clock is internally synchronized to the internal clock, and its frequency should be lower than the internal operating frequency divided by 4 (clk/4). note: to insure proper operation, the tc[3:0] bits should be changed only when the timer is disabled (i.e., when the te bit in the tcsr has been cleared). table 9-2 timer control bits bit settings mode characteristics tc3 tc2 tc1 tc0 mode number mode function tio clock 0000 0 timer and gpio gpio 1 internal 0001 1 timer pulse output internal 0010 2 timer toggle output internal 0011 3 event counter input external f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-11 9.3.4.5 inverter (inv) bit 8 the inverter (inv) bit affects the polarity definition of the incoming signal on the tio signal when tio is programmed as input. it also affects the polarity of the output pulse generated on the tio signal when tio is programmed as output. 0100 4 input width measurement input internal 0101 5 input period measurement input internal 0110 6 capture event input internal 0111 7 pulse width modulation (pwm) output internal 1000 8 reserved ? ? 1001 9 watchdog pulse output internal 1010 10 watchdog toggle output internal 1011 11 reserved ? ? 1100 12 reserved ? ? 1101 13 reserved ? ? 1110 14 reserved ? ? 1111 15 reserved ? ? note 1: the gpio function is enabled only if all of the tc[3:0] bits are 0. table 9-2 timer control bits (continued) bit settings mode characteristics tc3 tc2 tc1 tc0 mode number mode function tio clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-12 dsp56309um/d motorola triple timer module triple timer module programming model the inverter bit operation is described below in table 9-3 . table 9-3 inverter (inv) bit operation mode tio programmed as input tio programmed as output inv = 0 inv = 1 inv = 0 inv = 1 0 gpio signal on the tio signal read directly gpio signal on the tio signal inverted bit written to gpio put on tio signal directly bit written to gpio inverted and put on tio signal 1 counter is incremented on the rising edge of the signal from the tio signal counter is incremented on the falling edge of the signal from the tio signal ?? 2 counter is incremented on the rising edge of the signal from the tio signal counter is incremented on the falling edge of the signal from the tio signal tcrx output put on tio signal directly tcrx output inverted and put on tio signal 3 counter is incremented on the rising edge of the signal from the tio signal counter is incremented on the falling edge of the signal from the tio signal ?? 4 width of the high input pulse is measured width of the low input pulse is measured ?? 5 period is measured between the rising edges of the input signal period is measured between the falling edges of the input signal ?? 6 event is captured on the rising edge of the signal from the tio signal event is captured on the falling edge of the signal from the tio signal ?? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-13 the inv bit is cleared by a hardware reset signal or a software reset instruction. the inv bit affects both the timer and gpio modes. to insure correct operation, this bit should be changed only when one or both of the following conditions is true: the timer has been disabled by clearing the te bit in the tcsr. the timer is in gpio mode. the inv bit does not affect the polarity of the prescaler source when the tio is used as input to the prescaler. 9.3.4.6 timer reload mode (trm) bit 9 the trm bit controls the counter preload operation. in timer (0e3) and watchdog (9e10) modes, the counter is preloaded with the tlr value after the te bit is set and the first internal or external clock signal is received. if the trm bit is set, the counter is reloaded each time after it reaches the value contained by the tcr. in pwm mode (7), the counter is reloaded each time counter overflow occurs. in measurement (4e5) modes, if the trm and the te bits are set, the counter is preloaded with the tlr value on each appropriate edge of the input signal. if the trm bit is cleared, the counter operates as a free running counter and is incremented on each incoming event. the trm bit is cleared by a hardware reset signal or a software reset instruction. 7 ? ? pulse generated by the timer has positive polarity pulse generated by the timer has negative polarity 9 ? ? pulse generated by the timer has positive polarity pulse generated by the timer has negative polarity 10 ? ? pulse generated by the timer has positive polarity. pulse generated by the timer has negative polarity table 9-3 inverter (inv) bit operation (continued) mode tio programmed as input tio programmed as output inv = 0 inv = 1 inv = 0 inv = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-14 dsp56309um/d motorola triple timer module triple timer module programming model 9.3.4.7 direction (dir) bit 11 the dir bit determines the behavior of the tio signal when it is used as a gpio signal. when the dir bit is set, the tio signal is an output; when the dir bit is cleared, the tio signal is an input. the tio signal can be used as a gpio signal only when all of the tc[3:0] bits are cleared. if any of the tc[3:0] bits are set, then the gpio function is disabled and the dir bit has no effect. the dir bit is cleared by a hardware reset signal or a software reset instruction. 9.3.4.8 data input (di) bit 12 the di bit reflects the value of the tio signal. if the inv bit is set, the value of the tio signal is inverted before it is written to the di bit. if the inv bit is cleared, the value of the tio signal is written directly to the di bit. di is cleared by a hardware reset signal or a software reset instruction. 9.3.4.9 data output (do) bit 13 the do bit is the source of the tio value when it is a data output signal. the tio signal is data output when gpio mode is enabled and dir is set. a value written to the do bit is written to the tio signal. if the inv bit is set, the value of the do bit is inverted when written to the tio signal. when the inv bit is cleared, the value of the do bit is written directly to the tio signal. when gpio mode is disabled, writing the do bit has no effect. the do bit is cleared by a hardware reset signal or a software reset instruction. 9.3.4.10 prescaler clock enable (pce) bit 15 the pce bit is used to select the prescaler clock as the timer source clock. when the pce bit is cleared, the timer uses either an internal (clk/2) signal or an external (tio) signal as its source clock. when the pce bit is set, the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. to insure proper operation, the pce bit should be changed only when the timer is disabled (when the te bit is cleared). which source clock is used for the prescaler is determined by the ps[1:0] bits of the tplr. a timer can be clocked by a prescaler clock that is derived from the tio of another timer. 9.3.4.11 timer overflow flag (tof) bit 20 the tof bit is set to indicate that counter overflow has occurred. this bit is cleared by writing a 1 to the tof bit. writing a 0 to the tof bit has no effect. the bit is also cleared when the timer overflow interrupt is serviced. the tof bit is cleared by a hardware reset signal, a software reset instruction, the stop instruction, or by clearing the te bit to disable the timer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module triple timer module programming model motorola dsp56309um/d 9-15 9.3.4.12 timer compare flag (tcf) bit 21 the tcf bit is set to indicate that the event count is complete. in the timer, pwm, and watchdog modes, the tcf bit is set when (n e m + 1) events have been counted. (n is the value in the compare register and m is the tlr value.) in measurement modes, the tcf bit is set when the measurement is completed. writing a 1 into the tcf bit clears this bit. writing a 0 into the tcf bit has no effect. the bit is also cleared when the timer compare interrupt is serviced. the tcf bit is cleared by a hardware reset signal, a software reset instruction, the stop instruction, or by clearing the te bit to disable the timer. note: the tof and tcf bits are cleared by writing a 1 to the specific bit. in order to insure that only the desired bit is cleared, do not use the bset command. the proper way to clear these bits is to write (using a movep instruction) a 1 to the flag to be cleared and a 0 to the other flag. 9.3.4.13 tcsr reserved bits 3, 10, 14, 16-19, 22, 23 these reserved bits are read as 0 and should be written with 0 for future compatibility. 9.3.5 timer load register (tlr) the tlr is a 24-bit, write-only register. in all modes, the counter is preloaded with the tlr value after the te bit in the tcsr is set and a first event occurs. in timer modes, if the timer reload mode (trm) bit in the tcsr is set, the counter is reloaded each time after it has reached the value contained by the timer compare register (tcpr) and the new event occurs. in measurement modes, if the trm bit in the tcsr is set and the te bit in the tcsr is set, the counter is reloaded with the value in the tlr on each appropriate edge of the input signal. in pwm modes, if the trm bit in the tcsr is set, the counter is reloaded each time after it has overflowed and the new event occurs. in watchdog modes, if the trm bit in the tcsr is set, the counter is reloaded each time after it has reached the value contained by the tcpr and the new event occurs. in this mode, the counter is also reloaded whenever the tlr is written with a new value while the te bit in the tcsr is set. in all modes, if the trm bit in the tcsr is cleared (trm = 0), the counter operates as a free-running counter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-16 dsp56309um/d motorola triple timer module timer operational modes 9.3.6 timer compare register (tcpr) the tcpr is a 24-bit, read/write register that contains the value to be compared to the counter value. these two values are compared every timer clock after the te bit in the tcsr is set. when the values match, the timer compare flag (tcf) bit is set and an interrupt is generated if interrupts are enabled (if the timer compare interrupt enable (tcie) bit in the tcsr is set). the tcpr is ignored in measurement modes. 9.3.7 timer count register (tcr) the timer count register (tcr) is a 24-bit, read-only register. in timer and watchdog modes, the counter?s contents can be read at any time by reading the tcr register. in measurement modes, the tcr is loaded with the current value of the counter on the appropriate edge of the input signal, and its value can be read to determine the width, period, or delay of the leading edge of the input signal. when the timer is in measurement modes, the tio signal is used for the input signal. 9.4 timer operational modes each timer has these operational modes to meet a variety of system requirements: timer e gpio, mode 0: internal timer interrupt generated by the internal clock e pulse, mode 1: external timer pulse generated by the internal clock e toggle, mode 2: output timing signal toggled by the internal clock e event counter, mode 3: internal timer interrupt generated by an external clock measurement e input width, mode 4: input pulse width measurement e input pulse, mode 5: input signal period measurement e capture, mode 6: capture external signal pwm, mode 7: pulse width modulation watchdog e pulse, mode 9: output pulse, internal clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-17 e toggle, mode 10: output toggle, internal clock these modes are described in detail below. timer modes are selected by setting the tc[3:0] bits in the tcsr. table 9-2 on page 9-10 shows how the different timer modes are selected by setting the bits in the tcsr. the table also shows the tio signal direction and the clock source for each timer mode. that table summarizes these modes, and the following paragraphs describe these modes in detail. note: to insure proper operation, the tc[3:0] bits should be changed only when the timer is disabled (i.e., when the te bit in the tcsr is cleared). 9.4.1 timing modes the following timing modes are provided: timer gpio timer pulse timer toggle event counter 9.4.1.1 timer gpio (mode 0) in this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare interrupt is enabled). set the te bit to clear the counter and enable the timer. load the value the timer is to count into the tcpr. the counter is loaded with the tlr value when the first timer clock signal is received. the timer clock can be taken from either the dsp56309 clock divided by two (clk/2) or from the prescaler clock output. each subsequent clock signal increments the counter. when the counter equals the tcpr value, the tcf bit in tcsr is set, and a compare interrupt is generated if the tcie bit is set. if the trm bit in the tcsr is set, the counter bit settings mode characteristics tc3 tc2 tc1 tc0 tio clock # function name 0000 gpio internal 0 timer gpio f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-18 dsp56309um/d motorola triple timer module timer operational modes is reloaded with the tlr value at the next timer clock and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock signal. this process is repeated until the timer is disabled (i.e., te is cleared). if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. 9.4.1.2 timer pulse (mode 1) in this mode, the timer generates an external pulse on its tio signal when the timer count reaches a pre-set value. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tcpr. the counter is loaded with the tlr value when the first timer clock signal is received. the tio signal is loaded with the value of the inv bit. the timer clock signal can be taken from either the dsp56309 clock divided by two (clk/2) or from the prescaler clock output. each subsequent clock signal increments the counter. when the counter matches the tcpr value, the tcf bit in tcsr is set and a compare interrupt is generated if the tcie bit is set. the polarity of the tio signal is inverted for one timer clock period. if the trm bit is set, the counter is loaded with the tlr value on the next timer clock and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock. this process is repeated until the te bit is cleared (disabling the timer). the counter contents can be read at any time by reading tcr. the value of the tlr sets the delay between starting the timer and the generation of the output pulse. to generate successive output pulses with a delay of x clocks between signals, the tlr value should be set to x/2 and the trm bit should be set. this process is repeated until the timer is disabled (i.e., te is cleared). bit settings mode characteristics tc3 tc2 tc1 tc0 tio clock # function name 0001 output internal 1 timer pulse f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-19 if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. 9.4.1.3 timer toggle (mode 2) in this mode, the timer periodically toggles the polarity of the tio signal. set the te bit in the tcr to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tpcr. the counter is loaded with the tlr value when the first timer clock signal is received. the tio signal is loaded with the value of the inv bit. the timer clock signal can be taken from either the dsp56309 clock divided by two (clk/2) or from the prescaler clock output. each subsequent clock signal increments the counter. when the counter value matches the value in the tcpr, the polarity of the tio output signal is inverted. the tcf bit in the tcsr is set and a compare interrupt is generated if the tcie bit is set. if the trm bit is set, the counter is loaded with the value of the tlr when the next timer clock is received, and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock. this process is repeated until the te bit is cleared, disabling the timer. the counter contents can be read at any time by reading the tcr. the tlr value in the tcpr sets the delay between starting the timer and toggling the tio signal. to generate output signals with a delay of x clock cycles between toggles, the tlr value should be set to x/2, and the trm bit should be set. this process is repeated until the timer is disabled (i.e., te is cleared). if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. bit settings mode characteristics tc3 tc2 tc1 tc0 tio clock # function name 0010 output internal 0 timer toggle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-20 dsp56309um/d motorola triple timer module timer operational modes 9.4.1.4 timer event counter (mode 3) in this mode, the timer counts external events and issues an interrupt when a preset number of events is counted. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tpcr. the counter is loaded with the tlr value when the first timer clock signal is received. the timer clock signal can be taken from either the tio input signal or the prescaler clock output. each subsequent clock signal increments the counter. if an external clock is used, it must be internally synchronized to the internal clock, and its frequency must be less than the dsp56309 internal operating frequency divided by 4. the value of the inv bit in the tcsr determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. if the inv bit is set, high-to-low transitions increment the counter. if the inv bit is cleared, low-to-high transitions increment the counter. when the counter matches the value contained in the tcpr, the tcf bit in the tcsr is set, and a compare interrupt is generated if the tcie bit is set. if the trm bit is set, the counter is loaded with the value of the tlr when the next timer clock is received, and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock. this process is repeated until the timer is disabled (i.e., te is cleared). if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. 9.4.2 signal measurement modes the following signal measurement modes are provided: measurement input width bit settings mode characteristics tc3 tc2 tc1 tc0 tio clock # function name 0011 input external 3 timer event counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-21 measurement input period measurement capture 9.4.2.1 measurement accuracy the external signal is synchronized with the internal clock used to increment the counter. this synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle. 9.4.2.2 measurement input width (mode 4) in this mode, the timer counts the number of clocks that occur between opposite edges of an input signal. set the te bit to clear the counter and enable the timer. load the timer?s count value into the tlr. after the first appropriate transition (as determined by the inv bit) occurs on the tio input signal, the counter is loaded with the tlr value on the first timer clock signal received either from the dsp56309 clock divided by two (clk/2) or from the prescaler clock input. each subsequent clock signal increments the counter. if the inv bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on the tio signal. if the inv bit is cleared, the timer starts on the first low-to-high (0 to 1) transition on the tio signal. when the first transition opposite in polarity to the inv bit setting occurs on the tio signal, the counter stops. the tcf bit in the tcsr is set and a compare interrupt is generated if the tcie bit is set. the value of the counter (which measures the width of the tio pulse) is loaded into the tcr. the tcr can be read to determine the external signal pulse width. if the trm bit is set, the counter is loaded with the tlr value on the first timer clock received following the next valid transition occurring on the tio input signal and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock. bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 0100 4 input width measurement input internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-22 dsp56309um/d motorola triple timer module timer operational modes this process is repeated until the timer is disabled (i.e., te is cleared). if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. 9.4.2.3 measurement input period (mode 5) in this mode, the timer counts the period between the reception of signal edges of the same polarity across the tio signal. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tlr. the value of the inv bit determines whether the period is measured between consecutive low-to-high (0 to 1) transitions of tio or between consecutive high-to-low (1 to 0) transitions of tio. if inv is set, high-to-low signal transitions are selected. if inv is cleared, low-to-high signal transitions are selected. after the first appropriate transition occurs on the tio input signal, the counter is loaded with the tlr value on the first timer clock signal received from either the dsp56309 clock divided by two (clk/2) or the prescaler clock output. each subsequent clock signal increments the counter. on the next signal transition of the same polarity that occurs on tio, the tcf bit in the tcsr is set and a compare interrupt is generated if the tcie bit is set. the contents of the counter are loaded into the tcr. the tcr then contains the value of the time that elapsed between the two signal transitions on the tio signal. after the second signal transition, if the trm bit is set, the te bit is set to clear the counter and enable the timer. the counter is loaded with the tlr value on the first timer clock signal. each subsequent clock signal increments the counter. after the second signal transition, if the trm bit is set, the te bit is set to clear if the trm bit is cleared, the counter continues to be incremented on each timer clock. this process is repeated until the timer is disabled (i.e., te is cleared). if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 0101 5 input period measurement input internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-23 9.4.2.4 measurement capture (mode 6) in this mode, the timer counts the number of clocks that elapse between starting the timer and receiving an external signal. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tlr. when the first timer clock signal is received, the counter is loaded with the tlr value. the timer clock signal can be taken from either the dsp56309 clock divided by two (clk/2) or from the prescaler clock output. each subsequent clock signal increments the counter. at the first appropriate transition of the external clock detected on the tio signal, the tcf bit in the tcsr is set and, if the tcie bit is set, a compare interrupt is generated, the counter halts, and the contents of the counter are loaded into the tcr. the value of the tcr represents the delay between the setting of the te bit and the detection of the first clock edge signal on the tio signal. the value of the inv bit determines whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition of the external clock signals the end of the timing period. if the inv bit is set, a high-to-low transition signals the end of the timing period. if inv is cleared, a low-to-high transition signals the end of the timing period. if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. the counter contents can be read at any time by reading the tcr. bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 0110 6 capture measurement input internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-24 dsp56309um/d motorola triple timer module timer operational modes 9.4.3 pulse width modulation (pwm, mode 7) in this mode, the timer generates periodic pulses of a preset width. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tpcr. when first timer clock is received from either the dsp56309 internal clock divided by two (clk/2) or the prescaler clock output, the counter is loaded with the tlr value. each subsequent timer clock increments the counter. when the counter equals the value in the tcpr, the tio output signal is toggled and the tcf bit in the tcsr is set. the contents of the counter are placed into the tcr. if the tcie bit is set, a compare interrupt is generated. the counter continues to be incremented on each timer clock. if counter overflow has occurred, the tio output signal is toggled, the tof bit in tcsr is set, and an overflow interrupt is generated if the toie bit is set. if the trm bit is set, the counter is loaded with the tlr value on the next timer clock and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each timer clock. this process is repeated until the timer is disabled by clearing the te bit. tio signal polarity is determined by the value of the inv bit. when the counter is started by setting the te bit, the tio signal assumes the value of the inv bit. on each subsequent toggling of the tio signal, the polarity of the tio signal is reversed. for example, if the inv bit is set, the tio signal generates the following signal: 1010. if the inv bit is cleared, the tio signal generates the following signal: 0101. the counter contents can be read at any time by reading the tcr. the value of the tlr determines the output period ($ffffff - tlr + 1). the timer counter increments the initial tlr value and toggles the tio signal when the counter value exceeds $ffffff. bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 0111 7 pulse width modulation pwm output internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-25 the duty cycle of the tio signal is determined by the value in the tcpr. when the value in the tlr is incremented to a value equal to the value in the tcpr, the tio signal is toggled. the duty cycle is equal to ($ffffff e tcpr) divided by ($ffffff - tlr + 1). for a 50% duty cycle, the value of tcpr is equal to ($ffffff + tlr + 1) / 2. note: the value in tcpr must be greater than the value in tlr. 9.4.4 watchdog modes the following watchdog timer modes are provided: watchdog pulse watchdog toggle 9.4.4.1 watchdog pulse (mode 9) in this mode, the timer generates an external signal at a preset rate. the signal period is equal to the period of one timer clock. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tcpr. the counter is loaded with the tlr value on the first timer clock received from either the dsp56309 internal clock divided by two (clk/2) or the prescaler clock output. each subsequent timer clock increments the counter. when the counter matches the value of the tcpr, the tcf bit in the tcsr is set and a compare interrupt is generated if the tcie bit is also set. if the trm bit is set, the counter is loaded with the tlr value on the next timer clock and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each subsequent timer clock. this process is repeated until the timer is disabled (i.e., te is cleared). bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 1001 9 pulse watchdog output internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-26 dsp56309um/d motorola triple timer module timer operational modes if the counter overflows, the tof bit is set, and if toie is set, an overflow interrupt is generated. at the same time, a pulse is output on the tio signal with a pulse width equal to the timer clock period. the pulse polarity is determined by the value of the inv bit. if the inv bit is set, the pulse polarity is high (logical 1). if the inv bit is cleared, the pulse polarity is low (logical 0). the counter contents can be read at any time by reading the tcr. the counter is reloaded whenever the tlr is written with a new value while the te bit is set. note: in this mode, internal logic preserves the tio value and direction for an additional 2.5 internal clock cycles after a dsp56309 hardware reset signal is asserted. this insures that a valid reset signal is generated when the tio signal is used to reset the dsp56309. 9.4.4.2 watchdog toggle (mode 10) in this mode, the timer toggles an external signal after preset period. set the te bit to clear the counter and enable the timer. the value to which the timer is to count is loaded into the tpcr. the counter is loaded with the tlr value on the first timer clock received from either the dsp56309 internal clock divided by two (clk/2) or the prescaler clock output. each subsequent timer clock increments the counter. the tio signal is set to the value of the inv bit. when the counter equals the value in the tcpr, the tcf bit in the tcsr is set, and a compare interrupt is generated if the tcie bit is also set. if the trm bit is set, the counter is loaded with the tlr value on the next timer clock and the count is resumed. if the trm bit is cleared, the counter continues to be incremented on each subsequent timer clock. when counter overflow has occurred, the polarity of the tio output signal is inverted, the tof bit in the tcsr is set, and an overflow interrupt is generated if the toie bit is also set. the tio polarity is determined by the inv bit. the counter is reloaded whenever the tlr is written with a new value while the te bit is set. this process is repeated until the timer is disabled by clearing the te bit. the counter contents can be read at any time by reading the tcr register. bit settings mode characteristics tc3 tc2 tc1 tc0 mode name function tio clock 1010 10 toggle watchdog output internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . triple timer module timer operational modes motorola dsp56309um/d 9-27 note: in this mode, internal logic preserves the tio value and direction for an additional 2.5 internal clock cycles after a dsp56309 hardware reset signal is asserted. this insures that a valid reset signal is generated when the tio signal is used to reset the dsp56309. 9.4.5 reserved modes modes 8, 11, 12, 13, 14, and 15 are reserved. 9.4.6 special cases the following special cases apply during wait and stop state. 9.4.6.1 timer behavior during wait timer clocks are active during the execution of the wait instruction and timer activity is undisturbed. if a timer interrupt is generated, the dsp56309 leaves the wait state and services the interrupt. 9.4.6.2 timer behavior during stop during the execution of the stop instruction, the timer clocks are disabled, timer activity is stopped, and the tio signals are disconnected. any external changes that happen to the tio signals are ignored when the dsp56309 is in the stop state. to insure correct operation, the timers should be disabled before the dsp56309 is placed into the stop state. 9.4.7 dma trigger each timer can also be used to trigger dma transfers. for this to occur, a dma channel must be programmed to be triggered by a timer event. the timer issues a dma trigger on every event in all modes of operation. the dma channel does not have the capability to save multiple dma triggers generated by the timer. to insure that all dma triggers are serviced, the user must provide for the preceding dma trigger to be serviced before the next trigger is received by the dma channel. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9-28 dsp56309um/d motorola triple timer module timer operational modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 10-1 section 10 on-chip emulation module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-2 dsp56309um/d motorola on-chip emulation module 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 once module signals . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4 once controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5 once memory breakpoint logic. . . . . . . . . . . . . . . 10-9 10.6 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10.7 methods of entering debug mode . . . . . . . . . . . 10-16 10.8 pipeline information and ogdb register. . . . . 10-18 10.9 debugging resources . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.10 serial protocol description . . . . . . . . . . . . . . . . 10-22 10.11 target site debug system requirements . . . . 10-23 10.12 once module examples . . . . . . . . . . . . . . . . . . . . . . 10-23 10.13 jtag port/once module interaction . . . . . . . . . 10-29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module introduction motorola dsp56309um/d 10-3 10.1 introduction the dsp56300 core on-chip emulation (oncea) module provides a means of interacting with the dsp56300 core and its peripherals nonintrusively so that a user can examine registers, memory, or on-chip peripherals, thus facilitating hardware and software development on the dsp56300 core processor. to achieve this, special circuits and dedicated signals on the dsp56300 core are defined to avoid sacrificing any user-accessible on-chip resource. the once module resources can be accessed only after executing the jtag instruction enable_once. these resources are accessible even when the chip is operating in normal mode. see section 11?jtag port for a description of the jtag functionality and its relation to the once module. figure 10-1 shows the block diagram of the once module. 10.2 once module signals the once module controller functionality is accessed through the jtag port. there are no dedicated once module signals for the clock, data in, or data out. the jtag signals tck, tdi, and tdo are used to shift in and out data and instructions. see section 11.2?jtag signals on page 11-4 for the description of the jtag signals. to facilitate emulation-specific functions, one additional signal, called de , is provided on the dsp56309. figure 10-1 once module block diagram trace buffer breakpoint logic pipeline information trace logic once controller pab yab xab pdb pil gdb tdo trst tdi tck tags buffer control bus de aa0702 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-4 dsp56309um/d motorola on-chip emulation module debug event (de) 10.3 debug event (de ) the bidirectional open drain debug event signal (de ) provides a fast means of entering debug mode from an external command controller (when input), and a fast means of acknowledging the entering of debug mode to an external command controller (when output). the assertion of this signal by a command controller causes the dsp56300 core to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the tdi line. if the de signal is used to enter debug mode, then it must be deasserted after the once port responds with an acknowledge and before sending the first once command. the assertion of this signal by the dsp56300 core indicates that the dsp has entered debug mode and is waiting for commands to be entered from the tdi line. the de signal also facilitates multiple processor connections, as shown in figure 10-2 . in this way, the user can stop all the devices in the system when one of the devices enters debug mode. the user can also stop all the devices synchronously by asserting the de line. 10.4 once controller the once controller contains the following blocks: once command register (ocr), once decoder, and the status/control register. figure 10-3 illustrates a block diagram of the once controller. figure 10-2 once module multiprocessor configuration tdi tdo tdi tdo tdi tdo tdi tms tck de tdo trst aa0703 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once controller motorola dsp56309um/d 10-5 10.4.1 once command register (ocr) the ocr is an 8-bit shift register that receives its serial data from the tdi signal. it holds the 8-bit commands to be used as input for the once decoder. the ocr is shown in figure 10-4 . 10.4.1.1 register select (rs4ers0) bits 0e4 the register select bits define which register is source/destination for the read/write operation. see table 10-4 for the once register select encoding. 10.4.1.2 exit command (ex) bit 5 if the ex bit is set, leave debug mode and resume normal operation. the exit command is executed only if the go command is issued, and the operation is write to opdbr or figure 10-3 once controller block diagram figure 10-4 once command register once command register tdi tck status and control register tdo mode select once decoder isdebug isbkpt isswdbg isdr istrace register write register read update aa0704 ocr once command register reset = $00 write only r/w go ex rs4 rs3 rs2 rs1 rs0 76543210 aa0106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-6 dsp56309um/d motorola on-chip emulation module once controller read/write to no register selected. otherwise the ex bit is ignored. table 10-1 shows the definition of the ex bit. 10.4.1.3 go command (go) bit 6 if the go bit is set, execute the instruction that resides in the pil register. to execute the instruction, the core leaves debug mode. the core returns to debug mode immediately after executing the instruction if the ex bit is cleared. the core goes on to normal operation if the ex bit is set. the go command is executed only if the operation is write to opdbr or read/write to no register selected. otherwise the go bit is ignored. table 10-2 shows the definition of the go bit. 10.4.1.4 read/write command (r/w ) bit 7 the r/w bit, as shown in table 10-3 , specifies the direction of data transfer. table 10-4 shows how to encode once register selections. table 10-1 ex bit definition ex action 0 remain in debug mode 1 leave debug mode table 10-2 go bit definition go action 0 inactive?no action taken 1 execute instruction in pil table 10-3 r/w bit definition r/w action 0 write the data associated with the command into the register specified by rs4ers0. 1 read the data contained in the register specified by rs4ers0. table 10-4 once register select encoding rs[4:0] register selected 00000 once status and control register (oscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once controller motorola dsp56309um/d 10-7 00001 memory breakpoint counter (ombc) 00010 breakpoint control register (obcr) 00011 reserved address 00100 reserved address 00101 memory limit register 0 (omlr0) 00110 memory limit register 1 (omlr1) 00111 reserved address 01000 reserved address 01001 gdb register (ogdbr) 01010 pdb register (opdbr) 01011 pil register (opilr) 01100 pdb go-to register (for go to command) 01101 trace counter (otc) 01110 reserved address 01111 pab register for fetch (opabfr) 10000 pab register for decode (opabdr) 10001 pab register for execute (opabex) 10010 trace buffer and increment pointer 10011 reserved address 101xx reserved address 11xx0 reserved address 11x0x reserved address 110xx reserved address 11111 no register selected table 10-4 once register select encoding (continued) rs[4:0] register selected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-8 dsp56309um/d motorola on-chip emulation module once controller 10.4.2 once decoder (odec) the odec supervises the entire once module activity. it receives as input the 8-bit command from the ocr, a signal from jtag controller (indicating that 8 or 24 bits have been received and update of the selected data register must be performed), and a signal indicating that the core was halted. the odec generates all the strobes required for reading and writing the selected once registers. 10.4.3 once status and control register (oscr) the oscr is a 24-bit register used to enable trace mode and to indicate the cause of entering debug mode. the control bits are read/write while the status bits are read-only. the oscr bits are cleared by a hardware reset signal. the oscr is shown in figure 10-5 . 10.4.3.1 trace mode enable (tme) bit 0 the tme control bit, when set, enables trace mode. 10.4.3.2 interrupt mode enable (ime) bit 1 the ime control bit, when set, causes the chip to execute a vectored interrupt to the address vba:$06 instead of entering debug mode. 10.4.3.3 software debug occurrence (swo) bit 2 the swo bit is a read-only status bit that is set when debug mode is entered because of the execution of the debug or debugcc instruction with condition true. this bit is cleared when leaving debug mode. 10.4.3.4 memory breakpoint occurrence (mbo) bit 3 the mbo bit is a read-only status bit that is set when debug mode is entered because a memory breakpoint has been encountered. this bit is cleared when leaving debug mode. figure 10-5 once status and control register (oscr) once status and control register read/write os1 os0 to mbo swo ime tme 9876543210 23 indicates reserved bits, written as 0 for future compatibility aa0705 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once memory breakpoint logic motorola dsp56309um/d 10-9 10.4.3.5 trace occurrence (to) bit 4 the to bit is a read-only status bit that is set when debug mode is entered when the trace counter is zero while trace mode is enabled. this bit is cleared when leaving debug mode. 10.4.3.6 reserved ocsr bit 5 bit 5 is reserved for future use. it is read as 0 and should be written with 0 for future compatibility. 10.4.3.7 core status (os0, os1) bits 6-7 the os0, os1 bits are read-only status bits that provide core status information. by examining the status bits, the user can determine whether the chip has entered debug mode. examining swo, mbo, and to identifies the cause of entering debug mode. the user can also examine these bits and determine the cause why the chip has not entered debug mode after debug event (de ) assertion or as a result of the execution of the jtag debug request instruction (core waiting for the bus, stop or wait instruction, etc.). these bits are also reflected in the jtag instruction shift register, which allows the polling of the core status information at the jtag level. this is useful when the dsp56300 core executes the stop instruction (and therefore there are no clocks) to allow the reading of oscr. see table 10-5 for the definition of the os0eos1 bits. 10.4.3.8 reserved bits 8-23 bits 8e23 are reserved for future use. they are read as 0 and should be written with 0 for future compatibility. 10.5 once memory breakpoint logic memory breakpoints can be set on program memory or data memory locations. in addition, the breakpoint does not have to be in a specific memory address, but within an approximate address range where the program may be executing. this significantly increases the programmer?s ability to monitor what the program is doing in real time. table 10-5 core status bits description os1 os0 description 0 0 dsp56300 core is executing instructions 0 1 dsp56300 core is in wait or stop 1 0 dsp56300 core is waiting for bus 1 1 dsp56300 core is in debug mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-10 dsp56309um/d motorola on-chip emulation module once memory breakpoint logic the breakpoint logic, described in figure 10-6 , contains a latch for the addresses, which are registers that store the upper and lower address limit, address comparators, and a breakpoint counter. address comparators are useful in determining where a program may be getting lost or when data is being written where it should not be written. they are also useful in halting a program at a specific point to examine/change registers or memory. using address comparators to set breakpoints enables the user to set breakpoints in ram or rom and while in any operating mode. memory accesses are monitored according to the contents of the obcr as specified in section 10.5.6?once breakpoint control register (obcr) . figure 10-6 once memory breakpoint logic 0 memory address latch pab xab yab memory bus select memory limit register 1 address comparator 1 memory limit register 0 address comparator 0 tdi tdo tck breakpoint counter memory breakpoint selection dec breakpoint count = 0 occurred n,v n,v breakpoint control tdi tdo tck isbkpt aa0706 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once memory breakpoint logic motorola dsp56309um/d 10-11 10.5.1 once memory address latch (omal) the omal is a 16-bit register that latches the pab, xab or yab on every instruction cycle according to the mbs1embs0 bits in obcr. 10.5.2 once memory limit register 0 (omlr0) the omlr0 is a 16-bit register that stores the memory breakpoint limit. omlr0 can be read or written through the jtag port. before enabling breakpoints, omlr0 must be loaded by the external command controller. 10.5.3 once memory address comparator 0 (omac0) the omac0 compares the current memory address (stored in omal0) with the omlr0 contents. 10.5.4 once memory limit register 1 (omlr1) the omlr1 is a 16-bit register that stores the memory breakpoint limit. omlr1 can be read or written through the jtag port. before enabling breakpoints, omlr1 must be loaded by the external command controller. 10.5.5 once memory address comparator 1 (omac1) the omac1 compares the current memory address (stored in omal0) with the omlr1 contents. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-12 dsp56309um/d motorola on-chip emulation module once memory breakpoint logic 10.5.6 once breakpoint control register (obcr) the obcr is a 16-bit register used to define the memory breakpoint events. obcr can be read or written through the jtag port. all the bits of the obcr are cleared by a hardware reset signal. the obcr appears in figure 10-7 . 10.5.6.1 memory breakpoint select (mbs0embs1) bits 0e1 the mbs0embs1 bits enable memory breakpoints 0 and 1, allowing them to occur when a memory access is performed on p, x, or y space. see table 10-6 for the definition of the mbs0embs1 bits. 10.5.6.2 breakpoint 0 read/write select (rw00erw01) bits 2e3 the rw00erw01 bits define the memory breakpoint 0 to occur when a memory address access is performed for read, write, or both. see table 10-7 for the definition of the rw00erw01 bits. figure 10-7 once breakpoint control register (obcr) table 10-6 memory breakpoint 0 and 1 select table mbs1 mbs0 description 0 0 reserved 0 1 breakpoint on p access 1 0 breakpoint on x access 1 1 breakpoint on y access once breakpoint control register reset = $0010 read/write bt1 bt0 cc cc rw rw cc cc rw rw mb mb * * * * 11109876543210 15 14 13 12 * indicates reserved bits, written as 0 for future compatibility 10 11 11 10 01 00 01 00 s1 s0 aa0707 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once memory breakpoint logic motorola dsp56309um/d 10-13 10.5.6.3 breakpoint 0 condition code select (cc00ecc01) bits 4e5 the cc00ecc01 bits define the condition of the comparison between the current memory address (omal0) and the memory limit register 0 (omlr0). see table 10-8 for the definition of the cc00ecc01 bits. 10.5.6.4 breakpoint 1 read/write select (rw10erw11) bits 6e7 the rw10erw11 bits control define memory breakpoint 1 to occur when a memory address access is performed for read, write, or both. see table 10-9 for the definition of the rw10erw11 bits. table 10-7 breakpoint 0 read/write select table rw01 rw00 description 0 0 breakpoint disabled 0 1 breakpoint on write access 1 0 breakpoint on read access 1 1 breakpoint on read or write access table 10-8 breakpoint 0 condition select table cc01 cc00 description 0 0 breakpoint on not equal 0 1 breakpoint on equal 1 0 breakpoint on less than 1 1 breakpoint on greater than table 10-9 breakpoint 1 read/write select table rw11 rw10 description 0 0 breakpoint disabled 0 1 breakpoint on write access 1 0 breakpoint on read access 1 1 breakpoint read or write access f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-14 dsp56309um/d motorola on-chip emulation module once memory breakpoint logic 10.5.6.5 breakpoint 1 condition code select (cc10ecc11) bits 8e9 the cc10ecc11 bits define the condition of the comparison between the current memory address (omal0) and the once memory limit register 1 (omlr1). see table 10-10 for the definition of the cc10ecc11 bits. 10.5.6.6 breakpoint 0 and 1 event select (bt0ebt1) bits 10e11 the bt0ebt1 bits define the sequence between breakpoint 0 and 1. if the condition defined by bt0ebt1 is met, then the once breakpoint counter (ombc) is decremented. see table 10-11 for the definition of the bt0ebt1 bits. 10.5.6.7 once memory breakpoint counter (ombc) the ombc is a 16-bit counter that is loaded with a value equal to the number of times minus one that a memory access event should occur before a memory breakpoint is declared. the memory access event is specified by the obcr and by the memory limit registers. on each occurrence of the memory access event, the breakpoint counter is decremented. when the counter reaches 0 and a new occurrence takes place, the chip enters debug mode. the ombc can be read or written through the jtag port. every time that the limit register is changed or a different breakpoint event is selected in the obcr, the breakpoint counter must be written afterwards. this insures that the once table 10-10 breakpoint 1 condition select table cc11 cc10 description 0 0 breakpoint on not equal 0 1 breakpoint on equal 1 0 breakpoint on less than 1 1 breakpoint on greater than table 10-11 breakpoint 0 and 1 event select table bt1 bt0 description 0 0 breakpoint 0 and breakpoint 1 0 1 breakpoint 0 or breakpoint 1 1 0 breakpoint 1 after breakpoint 0 1 1 breakpoint 0 after breakpoint 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once trace logic motorola dsp56309um/d 10-15 breakpoint logic is reset and that no previous events can affect the new breakpoint event selected. the breakpoint counter is cleared by a hardware reset signal. 10.5.6.8 reserved bits 12-15 bits 12e15 are reserved for future use. they are read as 0 and should be written with 0 for future compatibility. 10.6 once trace logic using the once trace logic, execution of instructions in single or multiple steps is possible. the once trace logic causes the chip to enter debug mode after the execution of one or more instructions and wait for once commands from the debug serial port. the once trace logic block diagram is shown in figure 10-8 . trace mode has a counter associated with it so that more than one instruction can be executed before returning back to debug mode. the objective of the counter is to allow the user to take multiple instruction steps real time before entering debug mode. this feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops. the otc also enables the user to count the number of instructions executed in a code segment. to enable trace mode, the counter is loaded with a value, the program counter is set to the start location of the instruction(s) to be executed real time, the tme bit is set in the figure 10-8 once trace logic block diagram tdi tdo tck trace counter dec end of instruction count = 0 istrace aa0708 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-16 dsp56309um/d motorola on-chip emulation module methods of entering debug mode oscr, and the dsp56300 core exits debug mode by executing the appropriate command issued by the external command controller. upon exiting debug mode, the counter is decremented after each execution of an instruction. interrupts are serviceable then. moreover, all executed instructions, including fast interrupt services and the execution of each repeated instruction, cause the otc to be decremented. upon decrementing to 0, the dsp56300 core reenters debug mode, the trace occurrence bit (to) in the oscr register is set, the core status bits os[1:0] are set to 11, and the de signal is asserted to indicate that the dsp56300 core has entered debug mode and is requesting service. the once trace counter (otc) is a 16-bit counter that can be read or written through the jtag port. if n instructions are to be executed before entering debug mode, the otc should be loaded with n e 1. the otc is cleared by a hardware reset signal. 10.7 methods of entering debug mode entering debug mode is acknowledged by the chip by setting the core status bits os1 and os0 and asserting the de line. this informs the external command controller that the chip has entered debug mode and is waiting for commands. the dsp56300 core can disable the once module if the rom security option is implemented. if the rom security is implemented, the once module remains inactive until a write operation to the ogdbr is executed by the dsp56300 core. 10.7.1 external debug request during reset assertion holding the de line asserted during the assertion of reset causes the chip to enter debug mode. after receiving the acknowledge, the external command controller must negate the de line before sending the first command. note: in this case, the chip does not execute any instruction before entering debug mode. 10.7.2 external debug request during normal activity holding the de line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter debug mode. after receiving the acknowledge, the external command controller must negate the de line before sending f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module methods of entering debug mode motorola dsp56309um/d 10-17 the first command. this process is the same for any newly fetched instruction, including instructions fetched by the interrupt processing or instructions that will be aborted by the interrupt processing. note: in this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. 10.7.3 executing the jtag debug_request instruction executing the jtag instruction debug_request asserts an internal debug request signal. consequently, the chip finishes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. after entering debug mode, the core status bits os1 and os0 are set and the de line is asserted, thus acknowledging the external command controller that debug mode has been entered. 10.7.4 external debug request during stop executing the jtag instruction debug_request (or asserting de ) while the chip is in the stop state (i. e., has executed a stop instruction) causes the chip to exit the stop state and enter debug mode. after receiving the acknowledge, the external command controller must negate de before sending the first command. note: in this case, the chip completes the execution of the stop instruction and halts after the next instruction enters the instruction latch. 10.7.5 external debug request during wait executing the jtag instruction debug_request (or asserting de ) while the chip is in the wait state (i. e., has executed a wait instruction) causes the chip to exit the wait state and enter debug mode. after receiving the acknowledge, the external command controller must negate de before sending the first command. note: in this case, the chip completes the execution of the wait instruction and halts after the next instruction enters the instruction latch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-18 dsp56309um/d motorola on-chip emulation module pipeline information and ogdb register 10.7.6 software request during normal activity upon executing the dsp56300 core instruction debug (or debugcc when the specified condition is true), the chip enters debug mode after the instruction following the debug instruction has entered the instruction latch. 10.7.7 enabling trace mode when trace mode is enabled and the otc is greater than zero, the otc is decremented after each instruction execution. execution of an instruction when the value in the otc is 0 causes the chip to enter debug mode after completing the execution of the instruction. only instructions actually executed cause the otc to decrement. an aborted instruction does not decrement the otc and does not cause the chip to enter debug mode. 10.7.8 enabling memory breakpoints when the memory breakpoint mechanism is enabled with a breakpoint counter value of 0, the chip enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. in case of breakpoints on executed program memory fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. in case of breakpoints on accesses to x, y or program memory spaces by move instructions, the breakpoint is acknowledged after the completion of the instruction following the instruction that accessed the specified address. 10.8 pipeline information and ogdb register to restore the pipeline and to resume normal chip activity upon returning from debug mode, a number of on-chip registers store the chip pipeline status. figure 10-9 shows the block diagram of the pipeline information registers, with the exception of the pab registers, which appear in figure 10-10 on page 10-22. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module pipeline information and ogdb register motorola dsp56309um/d 10-19 10.8.1 once pdb register (opdbr) the opdbr is a 24-bit latch that stores the value of the program data bus generated by the last program memory access of the core before debug mode is entered. the opdbr register can be read or written through the jtag port. this register is affected by the operations performed during debug mode and must be restored by the external command controller when returning to normal mode. 10.8.2 once pil register (opilr) the opilr is a 24-bit latch that stores the value of the instruction latch before debug mode is entered. opilr can only be read through the jtag port. note: since the instruction latch is affected by the operations performed during debug mode, it must be restored by the external command controller when returning to normal mode. since there is no direct write access to the instruction latch, the task of restoring is accomplished by writing to opdbr with no-go and no-ex. in this case the data written on pdb is transferred into the instruction latch. figure 10-9 once pipeline information and gdb registers pdb register (opdbr) gdb register (ogdbr) tdi tdo tck pil register (opilr) pil pdb gdb aa0709 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-20 dsp56309um/d motorola on-chip emulation module debugging resources 10.8.3 once gdb register (ogdbr) the ogdbr is a 16-bit latch that can only be read through the jtag port. the ogdbr is not actually required for restoring the pipeline status but is required as a means of passing information between the chip and the external command controller. the ogdbr is mapped on the x internal i/o space at address $fffc. whenever the external command controller needs the contents of a register or memory location, it forces the chip to execute an instruction that brings that information to the ogdbr. then the contents of the ogdbr are delivered serially to the external command controller by the command read gdb register . 10.9 debugging resources to ease debugging activity and keep track of program flow, the dsp56300 core provides a number of on-chip dedicated resources. there are three read-only pab registers that give pipeline information when debug mode is entered, and a trace buffer that stores the address of the last instruction that was executed, as well as the addresses of the last 12 change-of-flow instructions. 10.9.1 once pab register for fetch (opabfr) the opabfr is a 16-bit register that stores the address of the last instruction whose fetch was started before debug mode was entered. the opabfr can only be read through the jtag port. this register is not affected by the operations performed during debug mode. 10.9.2 pab register for decode (opabdr) the opabdr is a 16-bit register that stores the address of the instruction currently on the pdb. this is the instruction whose fetch was completed before the chip has entered debug mode. the opabdr can only be read through the jtag port. this register is not affected by the operations performed during debug mode. 10.9.3 once pab register for execute (opabex) the opabex is a 16-bit register that stores the address of the instruction currently in the instruction latch. this is the instruction that would have been decoded and executed if f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module debugging resources motorola dsp56309um/d 10-21 the chip would not have entered debug mode. the opabex register can only be read through the jtag port. this register is not affected by the operations performed during debug mode. 10.9.4 trace buffer the trace buffer stores the addresses of the last 12 change-of-flow instructions that were executed, as well as the address of the last executed instruction. the trace buffer is implemented as a circular buffer containing 12 17-bit registers and one 4-bit counter. all the registers have the same address, but any read access to the trace buffer address causes the counter to increment, thus pointing to the next trace buffer register. the registers are serially available to the external command controller through their common trace buffer address. figure 10-10 on page 10-22 shows the block diagram of the trace buffer. the trace buffer is not affected by the operations performed during debug mode except for the trace buffer pointer increment when reading the trace buffer. when entering debug mode, the trace buffer counter is pointing to the trace buffer register containing the address of the last executed instructions. the first trace buffer read obtains the oldest address and the following trace buffer reads get the other addresses from the oldest to the newest, in order of execution. notes: 1. to insure trace buffer coherence, a complete set of 12 reads of the trace buffer must be performed. this is necessary due to the fact that each read increments the trace buffer pointer, thus pointing to the next location. after 12 reads, the pointer indicates the same location as before starting the read procedure. 2. on any change of flow instruction, the trace buffer stores both the address of the change of flow instruction, as well as the address of the target of the change of flow instruction. in the case of conditional change of flows, the address of the change of flow instruction is always stored (regardless of the fact that the change of flow is true or false), but if the conditional change of flow is false (i.e., not taken) the address of the target is not stored. in order to facilitate the program trace reconstruction, every trace buffer location has an additional ?invalid bit? (bit 24). if a conditional change of flow instruction has a ?condition false?, the invalid bit is set, thus marking this instruction as not taken. therefore, it is imperative to read 17 bits of data when reading the 12 trace buffer registers. since data is read lsb first, the invalid bit is the first bit to be read. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-22 dsp56309um/d motorola on-chip emulation module serial protocol description 10.10 serial protocol description to permit an efficient means of communication between the external command controller and the dsp56300 core chip, the following protocol is adopted. before starting any debugging activity, the external command controller has to wait for an acknowledge figure 10-10 once trace buffer fetch address (opabfr) pab decode address (opabdr) circular buffer pointer trace buffer shift register tdo tck trace buffer register 0 trace buffer register 1 trace buffer register 2 trace buffer register 11 execute address (opabex) tdi aa0710 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module target site debug system requirements motorola dsp56309um/d 10-23 on the de line indicating that the chip has entered debug mode. optionally the external command controller can poll the os1 and os0 bits in the jtag instruction shift register. the external command controller communicates with the chip by sending 8-bit commands that can be accompanied by 24 bits of data. both commands and data are sent or received lsb first. after sending a command, the external command controller should wait for the dsp56300 core chip to acknowledge execution of the command. the external command controller can send a new command only after the chip has acknowledged execution of the previous command. the once commands are classified as follows: read commands (when the chip delivers the required data) write commands (when the chip receives data and writes the data in one of the once registers) commands that do not have data transfers associated with them the commands are 8 bits long. the command formats are shown in figure 10-4 on page 10-5. 10.11 target site debug system requirements a typical debug environment consists of a target system where the dsp56300 core-based device resides in the user defined hardware. the jtag port interfaces to the external command controller over a 8-wire link consisting of the five jtag port wires, one once module wire, a ground, and a reset wire. the reset wire is optional and is only used to reset the dsp56300 core-based device and its associated circuitry. the external command controller acts as the medium between the dsp56300 core target system and a host computer. the external command controller circuit acts as a jtag port driver and host computer command interpreter. the controller issues commands based on the host computer inputs from a user interface program that communicates with the user. 10.12 once module examples following are some examples of debugging procedures. all these examples assume that the dsp is the only device in the jtag chain. if there is more than one device in the chain (additional dsps or other devices), the other devices can be forced to execute the jtag bypass instruction such as their effect in the serial stream will be one bit per additional f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-24 dsp56309um/d motorola on-chip emulation module once module examples device. the events such as select-dr, select-ir, update-dr, and shift-dr refer to bringing the jtag tap in the corresponding state. for a detailed description of the jtag protocol, see section 11?jtag port . 10.12.1 checking whether the chip has entered debug mode there are two methods to verify that the chip has entered debug mode: every time the chip enters debug mode, a pulse is generated on the de signal. a pulse is also generated every time the chip acknowledges the execution of an instruction while in debug mode. an external command controller can connect the de line to an interrupt signal in order to sense the acknowledge. an external command controller can poll the jtag instruction shift register for the status bits os[1:0]. when the chip is in debug mode, these bits are set to the value 11. note: in the following paragraphs, the ack notation denotes the operation performed by the command controller to check whether debug mode has been entered (either by sensing de or by polling jtag instruction shift register). 10.12.2 polling the jtag instruction shift register in order to poll the core status bits in the jtag instruction shift register the following sequence must be performed: 1. select shift-ir. passing through capture-ir loads the core status bits into the instruction shift register. 2. shift in enable_once. while shifting-in the new instruction, the captured status information is shifted-out. pass through update-ir. 3. return to run-test/idle. the external command controller can analyze the information shifted out and detect whether the chip has entered debug mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once module examples motorola dsp56309um/d 10-25 10.12.3 saving pipeline information the debugging activity is accomplished by means of dsp56300 core instructions supplied from the external command controller. therefore, the current state of the dsp56300 core pipeline must be saved prior to starting the debug activity and the state must be restored prior to returning to normal mode. here is the description of the save procedure (it assumes that enable_once has been executed and debug mode has been entered and verified, as described in section 10.12.1?checking whether the chip has entered debug mode ): 1. select shift-dr. shift in the read pdb. pass through update-dr. 2. select shift-dr. shift out the 24 bit opdb register. pass through update-dr. 3. select shift-dr. shift in the read pil. pass through update-dr. 4. select shift-dr. shift out the 24 bit opilr register. pass through update-dr. note that there is no need to verify acknowledge between steps 1 and 2, as well as 3 and 4, because completion is guaranteed by design. 10.12.4 reading the trace buffer an optional step during debugging activity is reading the information associated with the trace buffer in order to enable an external program to reconstruct the full trace of the executed program. in the following description of the read trace buffer procedure, it is assumed that all actions described in saving pipeline information have been executed. 1. select shift-dr. shift in the read pabfr. pass through update-dr. 2. select shift-dr. shift out the 16 bit opabfr register. pass through update-dr. 3. select shift-dr. shift in the read pabdr. pass through update-dr. 4. select shift-dr. shift out the 16 bit opabdr register. pass through update-dr. 5. select shift-dr. shift in the read pabex. pass through update-dr. 6. select shift-dr. shift out the 16 bit opabex register. pass through update-dr. 7. select shift-dr. shift in the read fifo. pass through update-dr. 8. select shift-dr. shift out the 17 bit fifo register. pass through update-dr. 9. repeat steps 7 and 8 for the entire fifo (12 times). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-26 dsp56309um/d motorola on-chip emulation module once module examples note: the user must read the entire fifo, since each read increments the fifo pointer, thus pointing to the next fifo location. at the end of this procedure, the fifo pointer points back to the beginning of the fifo. the information that has been read by the external command controller now contains the address of the newly fetched instruction, the address of the instruction currently on the pdb, the address of the instruction currently on the instruction latch, as well as the addresses of the last 12 instructions that have been executed and are change of flow. a user program can now reconstruct the flow of a full trace based on this information and on the original source code of the currently running program. 10.12.5 displaying a specified register to display a specified register, the dsp56300 must be in debug mode and all actions described in section 10.12.3?saving pipeline information have been executed. the sequence of actions is as follows: 1. select shift-dr. shift in the write pdb with go no-ex. pass through update-dr. 2. select shift-dr. shift in the 24-bit opcode: move reg, x:ogdb. pass through update-dr to actually write opdbr and thus begin executing the move instruction. 3. wait for dsp to reenter debug mode (wait for de or poll core status). 4. select shift-dr and shift in read gdb register. pass through update-dr. this step selects ogdbr as the data register for the read. 5. select shift-dr. shift out the ogdbr contents. pass through update-dr. wait for next command. 10.12.6 displaying x memory area starting at address $xxxx the dsp56309 must be in debug mode and all actions described in section 10.12.3?saving pipeline information must have been executed. since r0 is used as pointer for the memory, r0 is saved first. the sequence of actions is as follows: 1. select shift-dr. shift in the write pdb with go no-ex. pass through update-dr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module once module examples motorola dsp56309um/d 10-27 2. select shift-dr. shift in the 24-bit opcode: move r0, x:ogdb. pass through update-dr to actually write opdbr and thus begin executing the move instruction. 3. wait for dsp to reenter debug mode (wait for de or poll core status). 4. select shift-dr and shift in read gdb register. pass through update-dr. (this selects ogdbr as the data register for read.) 5. select shift-dr. shift out the ogdbr contents. pass through update-dr. r0 is now saved. 6. select shift-dr. shift in the write pdb with no-go no-ex. pass through update-dr. 7. select shift-dr. shift in the 24 bit opcode: move #$xxxx,r0. pass through update-dr to actually write opdbr. 8. select shift-dr. shift in the write pdb with go no-ex. pass through update-dr. 9. select shift-dr. shift in the second word of the 24 bit opcode: move #$xxxx,r0 (the $xxxx field). pass through update-dr to actually write opdbr and execute the instruction. r0 is loaded with the base address of the memory block to be read. 10. wait for dsp to reenter debug mode. (wait for de or poll core status.) 11. select shift-dr. shift in the write pdb with go no-ex. pass through update-dr. 12. select shift-dr. shift in the 24-bit opcode: move x:(r0)+, x:ogdb. pass through update-dr to actually write opdbr and thus begin executing the move instruction. 13. wait for dsp to reenter debug mode. (wait for de or poll core status.) 14. select shift-dr and shift in read gdb register. pass through update-dr. (this selects ogdbr as the data register for read.) 15. select shift-dr. shift out the ogdbr contents. pass through update-dr. the memory contents of address $xxxx have been read. 16. select shift-dr. shift in the no select with go no-ex. pass through update-dr. this reexecutes the same move x:(r0)+, x:ogdb instruction. 17. repeat from step 14 to complete the reading of the entire block. when finished, restore the original value of r0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-28 dsp56309um/d motorola on-chip emulation module once module examples 10.12.7 returning from debug to normal mode (same program) in this case, you have finished examining the current state of the machine, changed some of the registers, and wish to return and continue execution of the same program from the point where it stopped. therefore, you must restore the pipeline of the machine and enable normal instruction execution. the sequence of actions to do so is listed below: 1. select shift-dr. shift in the write pdb with no-go no-ex. pass through update-dr. 2. select shift-dr. shift in the 24 bits of saved pil (instruction latch value). pass through update-dr to actually write the instruction latch. 3. select shift-dr. shift in the write pdb with go and ex. pass through update-dr. 4. select shift-dr. shift in the 24 bits of saved pdb. pass through update-dr to actually write the pdb. at the same time the internally saved value of the pab is driven back from the pabfr register onto the pab, the odec releases the chip from debug mode, and the normal flow of execution is continued. 10.12.8 returning from debug to normal mode (new program) in this case, you have finished examining the current state of the machine, changed some of the registers, and wish to start the execution of a new program (the goto command). therefore, you must force a change-of-flow to the starting address of the new program ($xxxx). the sequence of actions to do so is listed below: 1. select shift-dr. shift in the write pdb with no-go no-ex. pass through update-dr. 1. select shift-dr. shift in the 24-bit $0af080 which is the opcode of the jump instruction. pass through update-dr to actually write the instruction latch. 2. select shift-dr. shift in the write pdb-go-to with go and ex. pass through update-dr. 3. select shift-dr. shift in the 16 bit of $xxxx. pass through update-dr to actually write the pdb. at this time the odec releases the chip from debug mode and the execution is started from the address $xxxx. note: if the device enters debug mode during a do loop, rep instruction, or other special cases such as interrupt processing, stop, wait, or conditional branching, you must first reset the dsp56300 and then proceed with the execution of the new program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module jtag port/once module interaction motorola dsp56309um/d 10-29 10.13 jtag port/once module interaction this subsection lists the details of the jtag port/once module interaction and tms sequencing required in order to achieve the communication described in section 10.12?once module examples . the external command controller can force the dsp56300 into debug mode by executing the jtag instruction debug_request. in order to check that the dsp56300 has entered debug mode, the external command controller must poll the status by reading the os[1:0] bits in the jtag instruction shift register. the tms sequencing appears in table 10-12 . the sequence to enable the once module appears in table 10-13 . after executing the jtag instructions debug_request and enable_once and after the core status was polled to verify that the chip is in debug mode, the pipeline saving procedure must take place. the tms sequencing for this procedure is depicted in table 10-12 . table 10-12 tms sequencing for debug_request step tms jtag port once module note a 0 run-test/idle idle ? b 1 select-dr-scan idle ? c 1 select-ir-scan idle ? d 0 capture-ir idle the status is sampled in the shifter. e 0 shift-ir idle the four bits of the jtag debug_request (0111) are shifted in while status is shifted out. .................................................................. e 0 shift-ir idle f 1 exit1-ir idle ? g 1 update-ir idle the debug request is generated. h 1 select-dr-scan idle ? i 1 select-ir-scan idle j 0 capture-ir idle the status is sampled in the shifter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-30 dsp56309um/d motorola on-chip emulation module jtag port/once module interaction in step n the external command controller verifies that the os[1:0] bits have the value 11, indicating that the chip has entered debug mode. if the chip has not yet entered debug mode, the external command controller goes to step b, step c etc. until debug mode is acknowledged. k 0 shift-ir idle the four bits of the jtag debug_request (0111) are shifted in while status is shifted out. .................................................................. k 0 shift-ir idle l 1 exit1-ir idle m 1 update-ir idle n 0 run-test/idle idle this step is repeated, enabling an external command controller to poll the status. ................................................ n 0 run-test/idle idle table 10-13 tms sequencing for enable_once step tms jtag port once module note a 1 test-logic-reset idle ? b 0 run-test/idle idle ? c 1 select-dr-scan idle ? d 1 select-ir-scan idle ? e 0 capture-ir idle the core status bits are captured. f 0 shift-ir idle the four bits of the jtag enable_once instruction (0110) are shifted into the jtag instruction register while status is shifted out. g 0 shift-ir idle h 0 shift-ir idle i 0 shift-ir idle j 1 exit1-ir idle ? k 1 update-ir idle the once module is enabled. table 10-12 tms sequencing for debug_request (continued) step tms jtag port once module note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . on-chip emulation module jtag port/once module interaction motorola dsp56309um/d 10-31 l 0 run-test/idle idle this step can be repeated, enabling an external command controller to poll the status. ................................................ l 0 run-test/idle idle table 10-14 tms sequencing for reading pipeline registers step tms jtag port once module note a 0 run-test/idle idle ? b 1 select-dr-scan idle ? c 0 capture-dr idle ? d 0 shift-dr idle the eight bits of the once command read pil (10001011) are shifted in. .................................................................. d 0 shift-dr idle e 1 exit1-dr idle ? f 1 update-dr execute read pil the pil value is loaded in the shifter. g 1 select-dr-scan idle ? h 0 capture-dr idle ? i 0 shift-dr idle the 24 bits of the pil are shifted out (24 steps). .................................................................. i 0 shift-dr idle j 1 exit1-dr idle ? k 1 update-dr idle ? l 1 select-dr-scan idle ? m 0 capture-dr idle ? table 10-13 tms sequencing for enable_once (continued) step tms jtag port once module note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10-32 dsp56309um/d motorola on-chip emulation module jtag port/once module interaction during step v the external command controller stores the pipeline information. afterwards, it can proceed with the debug activities as requested by the user. n 0 shift-dr idle the eight bits of the once command read pdb (10001010) are shifted in. .................................................................. n 0 shift-dr idle o 1 exit1-dr idle ? p 1 update-dr execute read pdb pdb value is loaded in shifter. q 1 select-dr-scan idle ? r 0 capture-dr idle ? s 0 shift-dr idle the 24 bits of the pdb are shifted out (24 steps). .................................................................. s 0 shift-dr idle t 1 exit1-dr idle ? u 1 update-dr idle ? v 0 run-test/idle idle this step can be repeated, enabling an external command controller to analyze the information. ................................................ v 0 run-test/idle idle table 10-14 tms sequencing for reading pipeline registers (continued) step tms jtag port once module note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d 11-1 section 11 jtag port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-2 dsp56309um/d motorola jtag port 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2 jtag signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4 dsp56300 restrictions . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.5 dsp56309 boundary scan register . . . . . . . . . . . 11-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port introduction motorola dsp56309um/d 11-3 11.1 introduction the dsp56300 core provides a dedicated user-accessible test access port (tap) that is fully compatible with the i eee 1149.1 standard test access port and boundary scan architecture . problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the test technology committee of ieee and the jtag. the dsp56300 core implementation supports circuit-board test strategies based on this standard. the test logic includes a tap that consists of five dedicated signals, a 16-state controller, and three test data registers. a boundary scan register (bsr) links all device signals into a single shift register. the test logic, implemented utilizing static logic design, is independent of the device system logic. the dsp56300 core implementation provides the following capabilities: performs boundary scan operations to test circuit-board electrical continuity (extest) bypasses the dsp56300 core for a given circuit-board test by effectively reducing the bsr to a single cell (bypass) samples the dsp56300 core-based device system signals during operation and transparently shifts out the result in the bsr preloads values to output signals prior to invoking the extest instruction (sample/preload) disables the output drive to signals during circuit-board testing (hi-z) provides a means of accessing the once controller and circuits to control a target system (enable_once) provides a means of entering debug mode (debug_request) queries identification information (manufacturer, part number and version) from a dsp56300 core-based device (idcode) forces test data onto the outputs of a dsp56300 core-based device while replacing its boundary scan register in the serial data path with a single bit register (clamp) this section, which includes aspects of the jtag implementation that are specific to the dsp56300 core, is intended to be used with the supporting ieee 1149.1 document. the discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the dsp56300 core implementation. for internal details and applications of the standard, refer to the ieee 1149.1 document. figure 11-1 shows a block diagram of the tap port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-4 dsp56309um/d motorola jtag port jtag signals 11.2 jtag signals as described in the ieee 1149.1 document, the jtag port requires a minimum of four signals to support tdi, tdo, tck, and tms signals. the dsp56300 family also provides figure 11-1 tap block diagram boundary scan register bypass mux 4-bit instruction register tdo tap ctrl tdi tms tck 0 2 3 1 once logic id register trst decoder mux aa0113 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port jtag signals motorola dsp56309um/d 11-5 the optional trst signal. on the dsp56309, the debug event (de ) signal is provided for use by the once module; it is documented in section 10?on-chip emulation module . the signal functions are described in the following paragraphs. 11.2.1 test clock (tck) the tck signal is used to synchronize the test logic. 11.2.2 test mode select (tms) the tms signal is used to sequence the test controller?s state machine. the tms is sampled on the rising edge of tck, and it has an internal pull-up resistor. 11.2.3 test data input (tdi) serial test instruction and data are received through the test data input (tdi) signal. tdi is sampled on the rising edge of tck, and it has an internal pull-up resistor. 11.2.4 test data output (tdo) the tdo signal is the serial output for test instructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. 11.2.5 test reset (trst ) the trst signal is used to asynchronously initialize the test controller. the trst signal has an internal pullup resistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-6 dsp56309um/d motorola jtag port tap controller 11.3 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the state machine is shown in figure 11-2 . the tap controller responds to changes at the tms and tck signals. transitions from one state to another occur on the rising edge of tck. the value shown adjacent to each state transition represents the value of the tms signal sampled on the rising edge of tck signal. for a description of the tap controller states, refer to the ieee 1149.1 document. figure 11-2 tap controller state machine select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr test-logic-reset run-test/idle update-dr 1 0 0 1 0 1 1 0 1 1 0 0 1 0 select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 11 aa0114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port tap controller motorola dsp56309um/d 11-7 11.3.1 boundary scan register (bsr) the bsr in the dsp56309 jtag implementation contains bits for all device signal and clock signals and associated control signals. all dsp56309 bidirectional signals have a single register bit in the bsr for signal data; each such signal is controlled by an associated control bit in the bsr. the dsp56309 bsr bit definitions are described in table 11-2 on page 11-13. 11.3.2 instruction register the dsp56309 jtag implementation includes the three mandatory public instructions (extest, sample/preload, and bypass), and also supports the optional clamp instruction defined by ieee 1149.1. the hi-z public instruction provides the capability for disabling all device output drivers. the enable_once public instruction enables the jtag port to communicate with the once circuitry. the debug_request public instruction enables the jtag port to force the dsp56300 core into debug mode. the dsp56300 core includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. figure 11-3 shows the jtag instruction register. the four bits are used to decode the eight unique instructions shown in table 11-1 . all other encodings are reserved for future enhancements and are decoded as bypass. figure 11-3 jtag instruction register jtag instruction register (ir) b3 b2 b1 b0 aa0746 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-8 dsp56309um/d motorola jtag port tap controller the parallel output of the instruction register is reset to 0010 in the test-logic-reset controller state, which is equivalent to the idcode instruction. during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with 01 in the lsbs as required by the standard. the two msbs are loaded with the values of the core status bits os1 and os0 from the once controller. see section 10?on-chip emulation module for a description of the status bits. 11.3.2.1 extest (b[3:0] = 0000) the external test (extest) instruction selects the bsr. extest also asserts internal reset for the dsp56300 core system logic to force a predictable internal state while performing external boundary scan operations. by using the tap, the bsr is capable of the following: scanning user-defined values into the output buffers capturing values presented to input signals table 11-1 jtag instructions code instruction b3 b2 b1 b0 0000 extest 0001 sample/preload 0010 idcode 0011 clamp 0100 hi-z 0101 reserved 0110 enable_once 0111 debug_request 1 0 x x reserved 1 1 0 x reserved 1110 reserved 1111 bypass f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port tap controller motorola dsp56309um/d 11-9 controlling the direction of bidirectional signals controlling the output drive of tri-stateable output signals for more details on the function and use of the extest instruction, please refer to the ieee 1149.1 document. 11.3.2.2 sample/preload (b[3:0] = 0001) the sample/preload instruction provides two separate functions. first, it provides a means to obtain a snapshot of system data and control signals. the snapshot occurs on the rising edge of tck in the capture-dr controller state. the data can be observed by shifting it transparently through the bsr. note: because there is no internal synchronization between the jtag clock (tck) and the system clock (clk), the user must provide some form of external synchronization to achieve meaningful results. the second function of the sample/preload instruction is to initialize the bsr output cells prior to selection of extest. this initialization insures that known data appears on the outputs when entering the extest instruction. 11.3.2.3 idcode (b[3:0] = 0010) the idcode instruction selects the id register. this instruction is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the tap. figure 11-4 shows the id register configuration. one application of the id register is to distinguish the manufacturer(s) of components on a board when multiple sourcing is used. as more components emerge which conform to the ieee 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in figure 11-4 jtag id register 0 1 11 12 27 28 31 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 0 design core number chip derivative number 21 22 16 17 0 0 0 0 0 0 0 0 1 1 0 center number 0 0 0 1 0 manufacturer identity version information customer part number 1 aa0718 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-10 dsp56309um/d motorola jtag port tap controller each location. this information is also available for factory process monitoring and for failure mode analysis of assembled boards. motorola?s manufacturer identity is 00000001110. the customer part number consists of two parts: motorola design center number (bits 27:22) and a sequence number (bits 21:12). the sequence number is divided into two parts: core number (bits 21:17) and chip derivative number (bits 16:12). motorola semiconductor israel (msil) design center number is 000110 and dsp56300 core number is 00001. once the idcode instruction is decoded, it selects the id register, which is a 32-bit data register. since the bypass register loads a logical 0 at the start of a scan cycle, whereas the id register loads a logical 1 into its lsb, examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from test-logic-reset controller state shows whether such a register is included in the design. when the idcode instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic as required by the ieee 1149.1 standard. 11.3.2.4 clamp (b[3:0] = 0011) the clamp instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction that selects the 1-bit bypass register as the serial path between tdi and tdo while allowing signals driven from the component signals to be determined from the bsr. during testing of ics on pcb, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. the extest instruction could be used for this purpose, but because it selects the bsr, the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. since the clamp instruction allows guarding values to be applied using the bsr of the appropriate ics while selecting their bypass registers, it allows much faster testing than does the extest instruction. data in the boundary scan cell remains unchanged until a new instruction is shifted in or the jtag state machine is set to its reset state. the clamp instruction also asserts internal reset for the dsp56300 core system logic to force a predictable internal state while performing external boundary scan operations. 11.3.2.5 hi-z (b[3:0] = 0100) the hi-z instruction is not included in the ieee 1149.1 standard. it is provided as a manufacturer?s optional public instruction to prevent having to backdrive the output signals during circuit-board testing. when hi-z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). the instruction selects the bypass register. the hi-z instruction also asserts internal reset for the dsp56300 core system logic to force a predictable internal state while performing external boundary scan operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port tap controller motorola dsp56309um/d 11-11 11.3.2.6 enable_once(b[3:0] = 0110) the enable_once instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction to allow you to perform system debug functions. when the enable_once instruction is decoded the tdi and tdo signals are connected directly to the once registers. the particular once register connected between tdi and tdo at a given time is selected by the once controller depending on the once instruction being currently executed. all communication with the once controller is done through the select-dr-scan path of the jtag tap controller. see section 10?on-chip emulation module for more information. 11.3.2.7 debug_request(b[3:0] = 0111) the debug_request instruction is not included in the ieee 1149.1 standard. it is provided as a public instruction to allow you to generate a debug request signal to the dsp56300 core. when the debug_request instruction is decoded, the tdi and tdo signals are connected to the instruction registers. due to the fact that in the capture-ir state of the tap the once status bits are captured in the instruction shift register, the external jtag controller must continue to shift-in the debug_request instruction while polling the status bits that are shifted-out until debug mode is entered (acknowledged by the combination 11 on os1eos0). after the acknowledgment of debug mode is received, the external jtag controller must issue the enable_once instruction to allow the user to perform system debug functions. 11.3.2.8 bypass (b[3:0] = 1111) the bypass instruction selects the single-bit bypass register, as shown in figure 11-5 . this choice creates a shift-register path from tdi to the bypass register, and finally to tdo, circumventing the bsr. this instruction is used to enhance test efficiency when a component other than the dsp56300 core-based device becomes the device under test. when the bypass register is selected by the current instruction, the shift-register stage is set to a logical 0 on the rising edge of tck in the capture-dr controller state. therefore, the first bit shifted out after selecting the bypass register is always a logical 0. figure 11-5 bypass register 1 1 mux g1 c d to tdo from tdi 0 shift dr clockdr aa0115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-12 dsp56309um/d motorola jtag port dsp56300 restrictions 11.4 dsp56300 restrictions the control afforded by the output enable signals using the bsr and the extest instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. you must avoid situations in which the dsp56300 core output drivers are enabled into actively driven networks. in addition, the extest instruction can be performed only after power-up or a regular hardware reset signal while extal was provided. then during the execution of extest, extal can remain inactive. there are two constraints related to the jtag interface. first, the tck input does not include an internal pullup resistor and should not be left unconnected. the second constraint is to insure that the jtag test logic is kept transparent to the system logic by forcing the tap into the test-logic-reset controller state, using either of two methods. during power-up, trst must be externally asserted to force the tap controller into this state. after power-up is concluded, tms must be sampled as a logical 1 for five consecutive tck rising edges. if tms either remains unconnected or is connected to v cc , then the tap controller cannot leave the test-logic-reset state, regardless of the state of tck. the dsp56300 core features a low-power stop mode, which is invoked using the stop instruction. the interaction of the jtag interface with low-power stop mode is as follows: 1. the tap controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. leaving the tap controller test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tck input is not blocked in low-power stop mode. to consume minimal power, the tck input should be externally connected to v cc or gnd. 3. the tms and tdi signals include on-chip pullup resistors. in low-power stop mode, these two signals should remain either unconnected or connected to v cc to achieve minimal power consumption. since during stop mode all dsp56309 core clocks are disabled, the jtag interface provides the means of polling the device status (sampled in the capture-ir state). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port dsp56309 boundary scan register motorola dsp56309um/d 11-13 11.5 dsp56309 boundary scan register table 11-2 provides a listing of the contents of the bsr for the dsp56309. table 11-2 dsp56309 bsr bit definitions bit # cell type signal name signal type bsr cell type 0 bc_1 moda input data 1 bc_1 modb input data 2 bc_1 modc input data 3 bc_1 modd input data 4 bc_6 d23 input/output data 5 bc_6 d22 input/output data 6 bc_6 d21 input/output data 7 bc_6 d20 input/output data 8 bc_6 d19 input/output data 9 bc_6 d18 input/output data 10 bc_6 d17 input/output data 11 bc_6 d16 input/output data 12 bc_6 d15 input/output data 13 bc_1 d[23:12] ? control 14 bc_6 d14 input/output data 15 bc_6 d13 input/output data 16 bc_6 d12 input/output data 17 bc_6 d11 input/output data 18 bc_6 d10 input/output data 19 bc_6 d9 input/output data 20 bc_6 d8 input/output data 21 bc_6 d7 input/output data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-14 dsp56309um/d motorola jtag port dsp56309 boundary scan register 22 bc_6 d6 input/output data 23 bc_6 d5 input/output data 24 bc_6 d4 input/output data 25 bc_6 d3 input/output data 26 bc_1 d[11:0] ? control 27 bc_6 d2 input/output data 28 bc_6 d1 input/output data 29 bc_6 d0 input/output data 30 bc_2 a15 output 2 data 31 bc_2 a14 output 2 data 32 bc_2 a13 output 2 data 33 bc_2 a12 output 2 data 34 bc_2 a11 output 2 data 35 bc_2 a10 output 2 data 36 bc_2 a9 output 2 data 37 bc_2 a8 output 2 data 38 bc_2 a7 output 2 data 39 bc_2 a6 output 2 data 40 bc_2 a5 output 2 data 41 bc_2 a4 output 2 data 42 bc_2 a3 output 2 data 43 bc_2 a2 output 2 data 44 bc_2 a1 output 2 data 45 bc_2 a0 output 2 data table 11-2 dsp56309 bsr bit definitions (continued) bit # cell type signal name signal type bsr cell type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port dsp56309 boundary scan register motorola dsp56309um/d 11-15 46 bc_2 mcs output data 47 bc_2 rd output data 48 bc_2 wr output data 49 bc_2 at output data 50 bc_2 clkout output data 51 bc_1 extal input data 52 bc_1 reset input data 53 bc_1 had0 ? control 54 bc_6 had0 input/output data 55 bc_1 had1 ? control 56 bc_6 had1 input/output data 57 bc_1 had2 ? control 58 bc_6 had2 input/output data 59 bc_1 had3 ? control 60 bc_6 had3 input/output data 61 bc_1 had4 ? control 62 bc_6 had4 input/output data 63 bc_1 had5 ? control 64 bc_6 had5 input/output data 65 bc_1 had6 ? control 66 bc_6 had6 input/output data 67 bc_1 had7 ? control 68 bc_6 had7 input/output data 69 bc_1 has/a0 ? control table 11-2 dsp56309 bsr bit definitions (continued) bit # cell type signal name signal type bsr cell type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-16 dsp56309um/d motorola jtag port dsp56309 boundary scan register 70 bc_6 has/a0 input/output data 71 bc_1 ha8/a1 ? control 72 bc_6 ha8/a1 input/output data 73 bc_1 ha9/a2 ? control 74 bc_6 ha9/a2 input/output data 75 bc_1 hcs/a10 ? control 76 bc_6 hcs/a10 input/output data 77 bc_1 tio0 ? control 78 bc_6 tio0 input/output data 79 bc_1 tio1 ? control 80 bc_6 tio1 input/output data 81 bc_1 tio2 ?- control 82 bc_6 tio2 input/output data 83 bc_1 hreq/trq ? control 84 bc_6 hreq/trq input/output data 85 bc_1 hack/rrq ? control 86 bc_6 hack/rrq input/output data 87 bc_1 hrw/rd ? control 88 bc_6 hrw/rd input/output data 89 bc_1 hds/wr ? control 90 bc_6 hds/wr input/output data 91 bc_1 sck0 ? control 92 bc_6 sck0 input/output data 93 bc_1 sck1 ? control table 11-2 dsp56309 bsr bit definitions (continued) bit # cell type signal name signal type bsr cell type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag port dsp56309 boundary scan register motorola dsp56309um/d 11-17 94 bc_6 sck1 input/output data 95 bc_1 gpio2 ? control 96 bc_6 gpio2 input/output data 97 bc_1 gpio1 ? control 98 bc_6 gpio1 input/output data 99 bc_1 gpio0 ? control 100 bc_6 gpio0 input/output data 101 bc_1 sc00 ? control 102 bc_6 sc00 input/output data 103 bc_1 sc10 ? control 104 bc_6 sc10 input/output data 105 bc_1 std0 ? control 106 bc_6 std0 input/output data 107 bc_1 srd0 ? control 108 bc_6 srd0 input/output data 109 bc_1 pinit ? control 110 bc_6 pinit input/output data 111 bc_1 de ? control 112 bc_6 de input/output data 113 bc_1 sc01 ? control 114 bc_6 sc01 input/output data 115 bc_1 sc02 ? control 116 bc_6 sc02 input/output data 117 bc_1 std1 ? control table 11-2 dsp56309 bsr bit definitions (continued) bit # cell type signal name signal type bsr cell type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11-18 dsp56309um/d motorola jtag port dsp56309 boundary scan register 118 bc_6 std1 input/output data 119 bc_1 srd1 ? control 120 bc_6 srd1 input/output data 121 bc_1 sc11 ? control 122 bc_6 sc11 input/output data 123 bc_1 sc12 ? control table 11-2 dsp56309 bsr bit definitions (continued) bit # cell type signal name signal type bsr cell type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d a-1 appendix a bootstrap programs ; bootstrap code for dsp56302 - (c) copyright 1995 motorola inc. ; revised june, 29 1995. ; ; bootstrap through the host interface, external eprom or sci. ; ; this is the bootstrap program contained in the dsp56302 192-word boot ; rom. this program can load any program ram segment from an external ; eprom, from the host interface or from the sci serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; if md:mc:mb:ma=1000 , then the boot rom is bypassed and the dsp56302 will ; start fetching instructions beginning with the address $8000 assuming that ; an external memory of sram type is used. the accesses will be performed ; using 31 wait states with no address attributes selected (default area). ; bootstrap code for dsp56309 - (c) copyright 1998 motorola inc. ; revised march, 1998. ; ; bootstrap through the host interface, external eprom or sci. ; ; this is the bootstrap program contained in the dsp56309 192-word boot ; rom. this program can load any program ram segment from an external ; eprom, from the host interface or from the sci serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; if md:mc:mb:ma=1000 , then the boot rom is bypassed and the dsp56309 will ; start fetching instructions beginning with the address $8000 assuming that ; an external memory of sram type is used. the accesses will be performed ; using 31 wait states with no address attributes selected (default area). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-2 dsp56309um/d motorola bootstrap programs ; bootstrap code for dsp56309 - (c) copyright 1997 motorola inc. ; revised march, 18 1997. ; ; bootstrap through the host interface, external eprom or sci. ; ; this is the bootstrap program contained in the dsp56309 192-word boot ; rom. this program can load any program ram segment from an external ; eprom, from the host interface or from the sci serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=x000, then the boot rom is bypassed and the dsp56309 ; will start fetching instructions beginning with address $c00000 (md=0) ; or $008000 (md=1) assuming that an external memory of sram type is ; used. the accesses will be performed using 31 wait states with no ; address attributes selected (default area). ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; operation modes md:mc:mb:ma=0001-0111 are reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1001, then it loads a program ram segment from consecutive ; byte-wide p memory locations, starting at p:$d00000 (bits 7-0). ; the memory is selected by the address attribute aa1 and is accessed with ; 31 wait states. ; the eprom bootstrap code expects to read 3 bytes ; specifying the number of program words, 3 bytes specifying the address ; to start loading the program words and then 3 bytes for each program ; word to be loaded. the number of words, the starting address and the ; program words are read least significant byte first followed by the ; mid and then by the most significant byte. ; the program words will be condensed into 24-bit words and stored in ; contiguous pram memory locations starting at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1010, then it loads the program ram from the sci interface. ; the number of program words to be loaded and the starting address must ; be specified. the sci bootstrap code expects to receive 3 bytes ; specifying the number of program words, 3 bytes specifying the address ; to start loading the program words and then 3 bytes for each program ; word to be loaded. the number of words, the starting address and the ; program words are received least significant byte first followed by the ; mid and then by the most significant byte. after receiving the ; program words, program execution starts in the same address where ; loading started. the sci is programmed to work in asynchronous mode ; with 8 data bits, 1 stop bit and no parity. the clock source is ; external and the clock frequency must be 16x the baud rate. ; after each byte is received, it is echoed back through the sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap programs motorola dsp56309um/d a-3 ; transmitter. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; operation mode md:mc:mb:ma=1011 is reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1100, then it loads the program ram from the host ; interface programmed to operate in the isa mode. ; the host isa bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. the program words will be stored in ; contiguous pram memory locations starting at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; the host interface bootstrap load program may be stopped by ; setting the host flag 0 (hf0). this will start execution of the loaded ; program from the specified starting address. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1101, then it loads the program ram from the host ; interface programmed to operate in the hc11 non multiplexed mode. ; ; the host hc11 bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. the program words will be stored in ; contiguous pram memory locations starting at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; the host interface bootstrap load program may be stopped by ; setting the host flag 0 (hf0). this will start execution of the loaded ; program from the specified starting address. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1110, then it loads the program ram from the host ; interface programmed to operate in the 8051 multiplexed bus mode, ; in double-strob pin configuration. ; the host 8051 bootstrap code expects accesses that are byte wide. ; the host 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; the program words will be stored in contiguous pram memory locations ; starting at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; the host interface bootstrap load program may be stopped by setting the ; host flag 0 (hf0). this will start execution of the loaded program from f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-4 dsp56309um/d motorola bootstrap programs ; the specified starting address. ; ; the base address of the hi08 in multiplexed mode is 0x80 and is not ; modified by the bootstrap code. all the address lines are enabled ; and should be connected accordingly. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; if md:mc:mb:ma=1111, then it loads the program ram from the host ; interface programmed to operate in the mc68302 (imp) bus mode, ; in single-strob pin configuration. ; the host mc68302 bootstrap code expects accesses that are byte wide. ; the host mc68302 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; the program words will be stored in contiguous pram memory locations ; starting at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; the host interface bootstrap load program may be stopped by setting the ; host flag 0 (hf0). this will start execution of the loaded program from ; the specified starting address. ; ;;;;;;;;;;;;;;;;;;;; memory equates ;;;;;;;;;;;;;;;;;;;;;;;; page 132,55,0,0,0 opt mex equaldata equ 1 ;; 1 if xram and yram are of equal ;; size and addresses, 0 otherwise. if (equaldata) start_dram equ 0 ;; 24k x and y ram length_dram equ $1c00 ;; same addresses else start_xram equ 0 ;; 7k xram length_xram equ $1c00 start_yram equ 0 ;; 7k yram length_yram equ $1c00 endif start_pram equ 0 ;; 20k pram length_pram equ $5000 ;; ;;;;;;;;;;;;;;;;;;;; general equates ;;;;;;;;;;;;;;;;;;;;;;;; ;; boot equ $d00000 ; this is the location in p memory ; on the external memory bus ; where the external byte-wide ; eprom would be located f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap programs motorola dsp56309um/d a-5 aarv equ $d00409 ; aar1 selects the eprom as ce~ ; mapped as p from $d00000 to ; $dfffff, active low ;; ;;;;;;;;;;;;;;;;;;;; dsp i/o registers ;;;;;;;;;;;;;;;;;;;;;;;; ;; m_pdrc equ $ffffbd ;; port c gpio data register m_prrc equ $ffffbe ;; port c direction register m_ssr equ $ffff93 ; sci status register m_stxl equ $ffff95 ; sci transmit data register (low) m_srxl equ $ffff98 ; sci receive data register (low) m_sccr equ $ffff9b ; sci clock control register m_scr equ $ffff9c ; sci control register m_pcre equ $ffff9f ; port e control register m_aar1 equ $fffff8 ; address attribute register 1 m_hpcr equ $ffffc4 ; host polarity control register m_hsr equ $ffffc3 ; host status rgister m_hrx equ $ffffc6 ; host recceive register hrdf equ $0 ; host receive data full hf0 equ $3 ; host flag 0 hen equ $6 ; host enable sck0 equ $3 ;; sck0 is bit #3 as gpio org pl:$ff0000,pl:$ff0000 ; bootstrap code starts at $ff0000 start clr a ; clear a jclr #3,omr,omr0xxx ; if md:mc:mb:ma=0xxx, go to omr0xxx jclr #2,omr,eprscild ; if md:mc:mb:ma=10xx, load from eprom/sci jclr #1,omr,omr1is0 ; if md:mc:mb:ma=110x, look for isa/hc11 jclr #0,omr,i8051hostld ; if md:mc:mb:ma=1110, load from 8051 host ; if md:mc:mb:ma=1111, load from mc68302 host ;======================================================================== ; this is the routine which loads a program through the hi08 host port ; the program is downloaded from the host mcu with the following rules: ; 1) 3 bytes - define the program length. ; 2) 3 bytes - define the address to which to start loading the program to. ; 3) 3n bytes (while n is any integer number) ; the program words will be stroed in contiguous pram memory locations starting ; at the specified starting address. ; after reading the program words, program execution starts from the same ; address where loading started. ; the host mcu may terminate the loading process by setting the hf1=0 and hf0=1. ; when the downloading is terminated, the program will start execution of the ; loaded program from the specified starting address. ; the hi08 boot rom program enables the following busses to download programs ; through the hi08 port: ; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-6 dsp56309um/d motorola bootstrap programs ; 1 - isa - dual strobes non-multiplexed bus with negative strobe ; pulses duale positive request ; 2 - hc11 - single strobe non-multiplexed bus with positive strobe ; pulse single negative request. ; 4 - i8051 - dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; 5 - mc68302 - single strobe non-multiplexed bus with negative strobe ; pulse single negative request. ;======================================================================== mc68302hostld movep #%0000000000111000,x:m_hpcr ; configure the following conditions: ; hap = 0 negative host acknowledge ; hrp = 0 negative host request ; hcsp = 0 negatice chip select input ; hd/hs = 0 single strobe bus (r/w~ and ds) ; hmux = 0 non multiplexed bus ; hasp = 0 (address strobe polarity has no ; meaning in non-multiplexed bus) ; hdsp = 0 negative data stobes polarity ; hrod = 0 host request is active when enabled ; spare = 0 this bit should be set to 0 for ; future compatability ; hen = 0 when the hpcr register is modified ; hen should be cleared ; haen = 1 host acknowledge is enabled ; hren = 1 host requests are enabled ; hcsen = 1 host chip select input enabled ; ha9en = 0 (address 9 enable bit has no ; meaning in non-multiplexed bus) ; ha8en = 0 (address 8 enable bit has no ; meaning in non-multiplexed bus) ; hgen = 0 host gpio pins are disabled bra bootstrap programs motorola dsp56309um/d a-11 else ;; x/y ram not symmetrical ;; write x memory clr a #start_xram,r0 ;; start of xram move #>length_xram,n0 ;; length of xram rep n0 mac x0,y0,a x1,x:(r0)+ ;; exercise mac, write xram ;; write y memory clr a #start_yram,r1 ;; start of yram move #>length_yram,n1 ;; length of yram rep n1 mac x1,y0,a x0,y:(r1)+ ;; exercise mac, write yram endif ;; write p memory clr a #start_pram,r2 ;; start of pram move #>length_pram,n2 ;; length of pram rep n2 move y0,p:(r2)+ ;; write pram ;; check memory contents if (equaldata) ;; x/y ram symmetrical ;; check dram clr a #start_dram,r0 ;; restore pointer, clear a do n0,_loopd move x:(r0),a1 ;; a0=a2=0 eor x1,a add a,b ;; accumulate error in b move y:(r0)+,a1 ;; a0=a2=0 eor x0,a add a,b ;; accumulate error in b _loopd else ;; x/y ram not symmetrical ;; check xram clr a #start_xram,r0 ;; restore pointer, clear a do n0,_loopx move x:(r0)+,a1 ;; a0=a2=0 eor x1,a add a,b ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 ;; restore pointer, clear a do n1,_loopy move y:(r1)+,a1 ;; a0=a2=0 eor x0,a add a,b ;; accumulate error in b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-12 dsp56309um/d motorola bootstrap programs _loopy endif ;; check pram clr a #start_pram,r2 ;; restore pointer, clear a do n2,_loopp move p:(r2)+,a1 ;; a0=a2=0 eor y0,a add a,b ;; accumulate error in b _loopp ;;--------------------------------------------------- ;; toggle pin if no errors, stop execution otherwise. ;;--------------------------------------------------- beq label1 bclr #sck0,x:m_pdrc ;; clear sck0 if error, enddo ;; terminate the loop normally bra b-2 dsp56309um/d motorola equates b.1 i/o equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 host interface (hi08) equates . . . . . . . . . . . . . . . . . b-3 b.3 sci equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.4 essi equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.5 exception processing equates. . . . . . . . . . . . . . . . b-7 b.6 timer module equates . . . . . . . . . . . . . . . . . . . . . . . . . b-9 b.7 direct memory access (dma) equates. . . . . . . . . b-10 b.8 phase-locked loop (pll) equates . . . . . . . . . . . . . b-12 b.9 bus interface unit (biu) equates . . . . . . . . . . . . . . b-13 b.10 interrupt equates . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-3 b.1 i/o equates ;------------------------------------------------------------------------ ; ;i/o port programming ; ;------------------------------------------------------------------------ ; register addresses m_hdr equ $ffffc9 ; host port gpio data register m_hddr equ $ffffc8 ; host port gpio direction register m_pcrc equ $ffffbf ; port c control register m_prrc equ $ffffbe ; port c direction register m_pdrc equ $ffffbd ; port c gpio data register m_pcrd equ $ffffaf ; port d control register m_prrd equ $ffffae ; port d direction data register m_pdrd equ $ffffad ; port d gpio data register m_pcre equ $ffff9f ; port e control register m_prre equ $ffff9e ; port e direction register m_pdre equ $ffff9d ; port e data register m_ogdb equ $fffffc ; once gdb register b.2 host interface (hi08) equates ;------------------------------------------------------------------------ host interface (hi08) equates ;------------------------------------------------------------------------ ; register addresses m_hcr equ $ffffc2 ; host control register m_hsr equ $ffffc3 ; host status register m_hpcr equ $ffffc4 ; host polarity control register m_hbar equ $ffffc5 ; host base address register m_hrx equ $ffffc6 ; host receive register m_htx equ $ffffc7 ; host transmit register ; hcr bits definition m_hrie equ $0 ; host receive interrupts enable m_htie equ $1 ; host transmit interrupt enable m_hcie equ $2 ; host command interrupt enable m_hf2 equ $3 ; host flag 2 m_hf3 equ $4 ; host flag 3 ; hsr bits definition m_hrdf equ $0 ; host receive data full m_htde equ $1 ; host receive data empty m_hcp equ $2 ; host command pending f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-4 dsp56309um/d motorola equates m_hf0 equ $3 ; host flag 0 m_hf1 equ $4 ; host flag 1 ; hpcr bits definition m_hgen equ $0 ; host port gpio enable m_ha8en equ $1 ; host address 8 enable m_ha9en equ $2 ; host address 9 enable m_hcsen equ $3 ; host chip select enable m_hren equ $4 ; host request enable m_haen equ $5 ; host acknowledge enable m_hen equ $6 ; host enable m_hod equ $8 ; host request open drain mode m_hdsp equ $9 ; host data strobe polarity m_hasp equ $a ; host address strobe polarity m_hmux equ $b ; host multiplexed bus select m_hd_hs equ $c ; host double/single strobe select m_hcsp equ $d ; host chip select polarity m_hrp equ $e ; host request polarity m_hap equ $f ; host acknowledge polarity b.3 sci equates ;------------------------------------------------------------------------ ;serial communications interface (sci) equates ;------------------------------------------------------------------------ ; register addresses m_stxh equ $ffff97 ; sci transmit data register (high) m_stxm equ $ffff96 ; sci transmit data register (middle) m_stxl equ $ffff95 ; sci transmit data register (low) m_srxh equ $ffff9a ; sci receive data register (high) m_srxm equ $ffff99 ; sci receive data register (middle) m_srxl equ $ffff98 ; sci receive data register (low) m_stxa equ $ffff94 ; sci transmit address register m_scr equ $ffff9c ; sci control register m_ssr equ $ffff93 ; sci status register m_sccr equ $ffff9b ; sci clock control register ; sci control register bit flags m_wds equ $7 ; word select mask (wds0-wds3) m_wds0 equ 0 ; word select 0 m_wds1 equ 1 ; word select 1 m_wds2 equ 2 ; word select 2 m_ssftd equ 3 ; sci shift direction m_sbk equ 4 ; send break m_wake equ 5 ; wakeup mode select f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-5 m_rwu equ 6 ; receiver wakeup enable m_woms equ 7 ; wired-or mode select m_scre equ 8 ; sci receiver enable m_scte equ 9 ; sci transmitter enable m_ilie equ 10 ; idle line interrupt enable m_scrie equ 11 ; sci receive interrupt enable m_sctie equ 12 ; sci transmit interrupt enable m_tmie equ 13 ; timer interrupt enable m_tir equ 14 ; timer interrupt rate m_sckp equ 15 ; sci clock polarity m_reie equ 16 ; sci error interrupt enable (reie) ; sci status register bit flags m_trne equ 0 ; transmitter empty m_tdre equ 1 ; transmit data register empty m_rdrf equ 2 ; receive data register full m_idle equ 3 ; idle line flag m_or equ 4 ; overrun error flag m_pe equ 5 ; parity error m_fe equ 6 ; framing error flag m_r8 equ 7 ; received bit 8 (r8) address ; sci clock control register m_cd equ $fff ; clock divider mask (cd0-cd11) m_cod equ 12 ; clock out divider m_scp equ 13 ; clock prescaler m_rcm equ 14 ; receive clock mode source bit m_tcm equ 15 ; transmit clock source bit b.4 essi equates ;------------------------------------------------------------------------ ;enhanced synchronous serial interface (essi) equates ;------------------------------------------------------------------------ ; register addresses of ssi0 m_tx00 equ $ffffbc ; ssi0 transmit data register 0 m_tx01 equ $ffffbb ; ssio transmit data register 1 m_tx02 equ $ffffba ; ssio transmit data register 2 m_tsr0 equ $ffffb9 ; ssi0 time slot register m_rx0 equ $ffffb8 ; ssi0 receive data register m_ssisr0 equ $ffffb7 ; ssi0 status register m_crb0 equ $ffffb6 ; ssi0 control register b m_cra0 equ $ffffb5 ; ssi0 control register a m_tsma0 equ $ffffb4 ; ssi0 transmit slot mask register a m_tsmb0 equ $ffffb3 ; ssi0 transmit slot mask register b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-6 dsp56309um/d motorola equates m_rsma0 equ $ffffb2 ; ssi0 receive slot mask register a m_rsmb0 equ $ffffb1 ; ssi0 receive slot mask register b ; register addresses of ssi1 m_tx10 equ $ffffac ; ssi1 transmit data register 0 m_tx11 equ $ffffab ; ssi1 transmit data register 1 m_tx12 equ $ffffaa ; ssi1 transmit data register 2 m_tsr1 equ $ffffa9 ; ssi1 time slot register m_rx1 equ $ffffa8 ; ssi1 receive data register m_ssisr1 equ $ffffa7 ; ssi1 status register m_crb1 equ $ffffa6 ; ssi1 control register b m_cra1 equ $ffffa5 ; ssi1 control register a m_tsma1 equ $ffffa4 ; ssi1 transmit slot mask register a m_tsmb1 equ $ffffa3 ; ssi1 transmit slot mask register b m_rsma1 equ $ffffa2 ; ssi1 receive slot mask register a m_rsmb1 equ $ffffa1 ; ssi1 receive slot mask register b ; ssi control register a bit flags m_pm equ $ff ; prescale modulus select mask (pm0-pm7) m_psr equ 11 ; prescaler range m_dc equ $1f000 ; frame rate divider control mask (dc0-dc7) m_alc equ 18 ; alignment control (alc) m_wl equ $380000 ; word length control mask (wl0-wl7) m_ssc1 equ 22 ; select sc1 as tr #0 drive enable (ssc1) ; ssi control register b bit flags m_of equ $3 ; serial output flag mask m_of0 equ 0 ; serial output flag 0 m_of1 equ 1 ; serial output flag 1 m_scd equ $1c ; serial control direction mask m_scd0 equ 2 ; serial control 0 direction m_scd1 equ 3 ; serial control 1 direction m_scd2 equ 4 ; serial control 2 direction m_sckd equ 5 ; clock source direction m_shfd equ 6 ; shift direction m_fsl equ $180 ; frame sync length mask (fsl0-fsl1) m_fsl0 equ 7 ; frame sync length 0 m_fsl1 equ 8 ; frame sync length 1 m_fsr equ 9 ; frame sync relative timing m_fsp equ 10 ; frame sync polarity m_ckp equ 11 ; clock polarity m_syn equ 12 ; sync/async control m_mod equ 13 ; ssi mode select m_sste equ $1c000 ; ssi transmit enable mask m_sste2 equ 14 ; ssi transmit #2 enable m_sste1 equ 15 ; ssi transmit #1 enable m_sste0 equ 16 ; ssi transmit #0 enable m_ssre equ 17 ; ssi receive enable m_sstie equ 18 ; ssi transmit interrupt enable m_ssrie equ 19 ; ssi receive interrupt enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-7 m_stlie equ 20 ; ssi transmit last slot interrupt enable m_srlie equ 21 ; ssi receive last slot interrupt enable m_steie equ 22 ; ssi transmit error interrupt enable m_sreie equ 23 ; ssi receive error interrupt enable ; ssi status register bit flags m_if equ $3 ; serial input flag mask m_if0 equ 0 ; serial input flag 0 m_if1 equ 1 ; serial input flag 1 m_tfs equ 2 ; transmit frame sync flag m_rfs equ 3 ; receive frame sync flag m_tue equ 4 ; transmitter underrun error flag m_roe equ 5 ; receiver overrun error flag m_tde equ 6 ; transmit data register empty m_rdf equ 7 ; receive data register full ; ssi transmit slot mask register a m_sstsa equ $ffff ; ssi transmit slot bits mask a (ts0-ts15) ; ssi transmit slot mask register b m_sstsb equ $ffff ; ssi transmit slot bits mask b (ts16-ts31) ; ssi receive slot mask register a m_ssrsa equ $ffff ; ssi receive slot bits mask a (rs0-rs15) ; ssi receive slot mask register b m_ssrsb equ $ffff ; ssi receive slot bits mask b (rs16-rs31) b.5 exception processing equates ;------------------------------------------------------------------------ exception processing equates ;------------------------------------------------------------------------ ; register addresses m_iprc equ $ffffff ; interrupt priority register core m_iprp equ $fffffe ; interrupt priority register peripheral ; interrupt priority register core (iprc) m_ial equ $7 ; irqa mode mask m_ial0 equ 0 ; irqa mode interrupt priority level (low) m_ial1 equ 1 ; irqa mode interrupt priority level (high) m_ial2 equ 2 ; irqa mode trigger mode m_ibl equ $38 ; irqb mode mask f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-8 dsp56309um/d motorola equates m_ibl0 equ 3 ; irqb mode interrupt priority level (low) m_ibl1 equ 4 ; irqb mode interrupt priority level (high) m_ibl2 equ 5 ; irqb mode trigger mode m_icl equ $1c0 ; irqc mode mask m_icl0 equ 6 ; irqc mode interrupt priority level (low) m_icl1 equ 7 ; irqc mode interrupt priority level (high) m_icl2 equ 8 ; irqc mode trigger mode m_idl equ $e00 ; irqd mode mask m_idl0 equ 9 ; irqd mode interrupt priority level ;(low) m_idl1 equ 10 ; irqd mode interrupt priority level ;(high) m_idl2 equ 11 ; irqd mode trigger mode m_d0l equ $3000 ; dma0 interrupt priority level mask m_d0l0 equ 12 ; dma0 interrupt priority level (low) m_d0l1 equ 13 ; dma0 interrupt priority level (high) m_d1l equ $c000 ; dma1 interrupt priority level mask m_d1l0 equ 14 ; dma1 interrupt priority level (low) m_d1l1 equ 15 ; dma1 interrupt priority level (high) m_d2l equ $30000 ; dma2 interrupt priority level mask m_d2l0 equ 16 ; dma2 interrupt priority level (low) m_d2l1 equ 17 ; dma2 interrupt priority level (high) m_d3l equ $c0000 ; dma3 interrupt priority level mask m_d3l0 equ 18 ; dma3 interrupt priority level (low) m_d3l1 equ 19 ; dma3 interrupt priority level (high) m_d4l equ $300000 ; dma4 interrupt priority level mask m_d4l0 equ 20 ; dma4 interrupt priority level (low) m_d4l1 equ 21 ; dma4 interrupt priority level (high) m_d5l equ $c00000 ; dma5 interrupt priority level mask m_d5l0 equ 22 ; dma5 interrupt priority level (low) m_d5l1 equ 23 ; dma5 interrupt priority level (high) ; interrupt priority register peripheral (iprp) m_hpl equ $3 ; host interrupt priority level mask m_hpl0 equ 0 ; host interrupt priority level (low) m_hpl1 equ 1 ; host interrupt priority level (high) m_s0l equ $c ; ssi0 interrupt priority level mask m_s0l0 equ 2 ; ssi0 interrupt priority level (low) m_s0l1 equ 3 ; ssi0 interrupt priority level (high) m_s1l equ $30 ; ssi1 interrupt priority level mask m_s1l0 equ 4 ; ssi1 interrupt priority level (low) m_s1l1 equ 5 ; ssi1 interrupt priority level (high) m_scl equ $c0 ; sci interrupt priority level mask m_scl0 equ 6 ; sci interrupt priority level (low) m_scl1 equ 7 ; sci interrupt priority level (high) m_t0l equ $300 ; timer interrupt priority level mask m_t0l0 equ 8 ; timer interrupt priority level (low) m_t0l1 equ 9 ; timer interrupt priority level (high) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-9 b.6 timer module equates ;--------------------------------------------------------------- ;timer module equates ;--------------------------------------------------------------- ; register addresses of timer0 m_tcsr0 equ $ffff8f ; timer0 control/status register m_tlr0 equ $ffff8e ; timer0 load register m_tcpr0 equ $ffff8d ; timer0 compare register m_tcr0 equ $ffff8c ; timer0 count register ; register addresses of timer1 m_tcsr1 equ $ffff8b ; timer1 control/status register m_tlr1 equ $ffff8a ; timer1 load register m_tcpr1 equ $ffff89 ; timer1 compare register m_tcr1 equ $ffff88 ; timer1 count register ; register addresses of timer2 m_tcsr2 equ $ffff87 ; timer2 control/status register m_tlr2 equ $ffff86 ; timer2 load register m_tcpr2 equ $ffff85 ; timer2 compare register m_tcr2 equ $ffff84 ; timer2 count register m_tplr equ $ffff83 ; timer prescaler load register m_tpcr equ $ffff82 ; timer prescaler count register ; timer control/status register bit flags m_te equ 0 ; timer enable m_toie equ 1 ; timer overflow interrupt enable m_tcie equ 2 ; timer compare interrupt enable m_tc equ $f0 ; timer control mask tc(3:0) m_inv equ 8 ; inverter bit m_trm equ 9 ; timer restart mode m_dir equ 11 ; direction bit m_di equ 12 ; data input m_do equ 13 ; data output m_pce equ 15 ; prescaled clock enable m_tof equ 20 ; timer overflow flag m_tcf equ 21 ; timer compare flag ; timer prescaler register bit flags m_ps equ $600000 ; prescaler source mask m_ps0 equ 21 m_ps1 equ 22 ; timer control bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-10 dsp56309um/d motorola equates m_tc0 equ 4 ; timer control 0 m_tc1 equ 5 ; timer control 1 m_tc2 equ 6 ; timer control 2 m_tc3 equ 7 ; timer control 3 b.7 direct memory access (dma) equates ;------------------------------------------------------------------------ ;direct memory access (dma) equates ;------------------------------------------------------------------------ ; register addresses of dma m_dstr equ $fffff4 ; dma status register m_dor0 equ $fffff3 ; dma offset register 0 m_dor1 equ $fffff2 ; dma offset register 1 m_dor2 equ $fffff1 ; dma offset register 2 m_dor3 equ $fffff0 ; dma offset register 3 ; register addresses of dma0 m_dsr0 equ $ffffef ; dma0 source address register m_ddr0 equ $ffffee ; dma0 destination address register m_dco0 equ $ffffed ; dma0 counter m_dcr0 equ $ffffec ; dma0 control register ; register addresses of dma1 m_dsr1 equ $ffffeb ; dma1 source address register m_ddr1 equ $ffffea ; dma1 destination address register m_dco1 equ $ffffe9 ; dma1 counter m_dcr1 equ $ffffe8 ; dma1 control register ; register addresses of dma2 m_dsr2 equ $ffffe7 ; dma2 source address register m_ddr2 equ $ffffe6 ; dma2 destination address register m_dco2 equ $ffffe5 ; dma2 counter m_dcr2 equ $ffffe4 ; dma2 control register ; register addresses of dma4 m_dsr3 equ $ffffe3 ; dma3 source address register m_ddr3 equ $ffffe2 ; dma3 destination address register m_dco3 equ $ffffe1 ; dma3 counter m_dcr3 equ $ffffe0 ; dma3 control register ; register addresses of dma4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-11 m_dsr4 equ $ffffdf ; dma4 source address register m_ddr4 equ $ffffde ; dma4 destination address register m_dco4 equ $ffffdd ; dma4 counter m_dcr4 equ $ffffdc ; dma4 control register ; register addresses of dma5 m_dsr5 equ $ffffdb ; dma5 source address register m_ddr5 equ $ffffda ; dma5 destination address register m_dco5 equ $ffffd9 ; dma5 counter m_dcr5 equ $ffffd8 ; dma5 control register ; dma control register m_dss equ $3 ; dma source space mask ;(dss0-dss1) m_dss0 equ 0 ; dma source memory space 0 m_dss1 equ 1 ; dma source memory space 1 m_dds equ $c ; dma destination space mask ;(dds-dds1) m_dds0 equ 2 ; dma destination memory space 0 m_dds1 equ 3 ; dma destination memory space 1 m_dam equ $3f0 ; dma address mode mask ;(dam5-dam0) m_dam0 equ 4 ; dma address mode 0 m_dam1 equ 5 ; dma address mode 1 m_dam2 equ 6 ; dma address mode 2 m_dam3 equ 7 ; dma address mode 3 m_dam4 equ 8 ; dma address mode 4 m_dam5 equ 9 ; dma address mode 5 m_d3d equ 10 ; dma three dimensional mode m_drs equ $f800 ; dma request source mask (drs0-drs4) m_dcon equ 16 ; dma continuous mode m_dpr equ $60000 ; dma channel priority m_dpr0 equ 17 ; dma channel priority level (low) m_dpr1 equ 18 ; dma channel priority level (high) m_dtm equ $380000 ; dma transfer mode mask ;(dtm2-dtm0) m_dtm0 equ 19 ; dma transfer mode 0 m_dtm1 equ 20 ; dma transfer mode 1 m_dtm2 equ 21 ; dma transfer mode 2 m_die equ 22 ; dma interrupt enable bit m_de equ 23 ; dma channel enable bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-12 dsp56309um/d motorola equates ; dma status register m_dtd equ $3f ;channel transfer done status mask m_dtd0 equ 0 ; dma channel transfer done status 0 m_dtd1 equ 1 ; dma channel transfer done status 1 m_dtd2 equ 2 ; dma channel transfer done status 2 m_dtd3 equ 3 ; dma channel transfer done status 3 m_dtd4 equ 4 ; dma channel transfer done status 4 m_dtd5 equ 5 ; dma channel transfer done status 5 m_dact equ 8 ; dma active state m_dch equ $e00 ; dma active channel mask ;(dch0dch2) m_dch0 equ 9 ; dma active channel 0 m_dch1 equ 10 ; dma active channel 1 m_dch2 equ 11 ; dma active channel 2 b.8 phase-locked loop (pll) equates ;--------------------------------------------------------------- ;phase locked loop (pll) equates ;--------------------------------------------------------------- ; register addresses of pll m_pctl equ $fffffd ; pll control register ; pll control register m_mf equ $fff ; multiplication factor bit mask (mf0-mf11) m_df equ $7000 ; division factor bit mask (df0-df2) m_xtlr equ 15 ; xtal range select bit m_xtld equ 16 ; xtal disable bit m_pstp equ 17 ; stop processing state bit m_pen equ 18 ; pll enable bit m_pcod equ 19 ; pll clock output disable bit m_pd equ $f00000 ; predivider factor bit mask (pd0-pd3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-13 b.9 bus interface unit (biu) equates ;--------------------------------------------------------------- ;bus interface unit (biu) equates ;--------------------------------------------------------------- ; register addresses of biu m_bcr equ $fffffb ; bus control register m_dcr equ $fffffa ; dram control register m_aar0 equ $fffff9 ; address attribute register 0 m_aar1 equ $fffff8 ; address attribute register 1 m_aar2 equ $fffff7 ; address attribute register 2 m_aar3 equ $fffff6 ; address attribute register 3 m_idr equ $fffff5 ; id register ; bus control register m_ba0w equ $1f ; area 0 wait control mask (ba0w0-ba0w4) m_ba1w equ $3e0 ; area 1 wait control mask (ba1w0-ba14) m_ba2w equ $1c00 ; area 2 wait control mask (ba2w0-ba2w2) m_ba3w equ $e000 ; area 3 wait control mask (ba3w0-ba3w3) m_bdfw equ $1f0000 ; default area wait control mask (bdfw0-bdfw4) m_bbs equ 21 ; bus state m_blh equ 22 ; bus lock hold m_brh equ 23 ; bus request hold ; dram control register m_bcw equ $3 ; in page wait states bit mask (bcw0-bcw1) m_brw equ $c ; out of page wait states bit mask (brw0-brw1) m_bps equ $300 ; dram page size bit mask (bps0-bps1) m_bple equ 11 ; page logic enable m_bme equ 12 ; mastership enable m_bre equ 13 ; refresh enable m_bstr equ 14 ; software triggered refresh m_brf equ $7f8000 ; refresh rate bits mask (brf0-brf7) m_brp equ 23 ; refresh prescaler ; address attribute registers m_bat equ $3 ; external access type and pin definition bits ; mask bat(1:0) m_baap equ 2 ; address attribute pin polarity m_bpen equ 3 ; program space enable m_bxen equ 4 ; x data space enable m_byen equ 5 ; y data space enable m_bam equ 6 ; address muxing m_bpac equ 7 ; packing enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-14 dsp56309um/d motorola equates m_bnc equ $f00 ; number of address bits to compare mask m_bac equ $fff000 ; address to compare bits mask bac(11:0) ; control and status bits in sr m_cp equ $c00000 ; mask for core-dma priority bits in sr m_ca equ 0 ; carry m_v equ 1 ; overflow m_z equ 2 ; zero m_n equ 3 ; negative m_u equ 4 ; unnormalized m_e equ 5 ; extension m_l equ 6 ; limit m_s equ 7 ; scaling bit m_i0 equ 8 ; interrupt mask bit 0 m_i1 equ 9 ; interrupt mask bit 1 m_s0 equ 10 ; scaling mode bit 0 m_s1 equ 11 ; scaling mode bit 1 m_sc equ 13 ; sixteen_bit compatibility m_dm equ 14 ; double precision multiply m_lf equ 15 ; do-loop flag m_fv equ 16 ; do-forever flag m_sa equ 17 ; sixteen-bit arithmetic m_ce equ 19 ; instruction cache enable m_sm equ 20 ; arithmetic saturation m_rm equ 21 ; rounding mode m_cp0 equ 22 ; bit 0 of priority bits in sr m_cp1 equ 23 ; bit 1 of priority bits in sr ; control and status bits in omr m_cdp equ $300 ; mask for core-dma priority bits in omr m_ma equ 0 ; operating mode a m_mb equ 1 ; operating mode b m_mc equ 2 ; operating mode c m_md equ 3 ; operating mode d m_ebd equ 4 ; external bus disable bit in omr m_sd equ 6 ; stop delay m_ms equ 7 ; memory switch bit in omr m_cdp0 equ 8 ; bit 0 of priority bits in omr m_cdp1 equ 9 ; bit 1 of priority bits in omr m_ben equ 10 ; burst enable m_tas equ 11 ; ta synchronize select m_brt equ 12 ; bus release timing m_ate equ 15 ; address tracing enable bit in omr. m_xys equ 16 ; stack extension space select bit in omr. m_eun equ 17 ; extended stack underflow flag in omr. m_eov equ 18 ; extended stack overflow flag in omr. m_wrp equ 19 ; extended wrap flag in omr. m_sen equ 20 ; stack extension enable bit in omr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . equates motorola dsp56309um/d b-15 b.10 interrupt equates ;*************************************************************** ; equates for dsp56309 interrupts ;************************************************************** ;--------------------------------------------------------------- ; non-maskable interrupts ;--------------------------------------------------------------- i_reset equ i_vec+$00 ; hardware reset i_stack equ i_vec+$02 ; stack error i_ill equ i_vec+$04 ; illegal instruction i_dbg equ i_vec+$06 ; debug request i_trap equ i_vec+$08 ; trap i_nmi equ i_vec+$0a ; non maskable interrupt ;--------------------------------------------------------------- ; interrupt request pins ;--------------------------------------------------------------- i_irqa equ i_vec+$10 ; irqa i_irqb equ i_vec+$12 ; irqb i_irqc equ i_vec+$14 ; irqc i_irqd equ i_vec+$16 ; irqd ;--------------------------------------------------------------- ; dma interrupts ;--------------------------------------------------------------- i_dma0 equ i_vec+$18 ; dma channel 0 i_dma1 equ i_vec+$1a ; dma channel 1 i_dma2 equ i_vec+$1c ; dma channel 2 i_dma3 equ i_vec+$1e ; dma channel 3 i_dma4 equ i_vec+$20 ; dma channel 4 i_dma5 equ i_vec+$22 ; dma channel 5 ;--------------------------------------------------------------- ; timer interrupts ;--------------------------------------------------------------- i_tim0c equ i_vec+$24 ; timer 0 compare i_tim0of equ i_vec+$26 ; timer 0 overflow i_tim1c equ i_vec+$28 ; timer 1 compare i_tim1of equ i_vec+$2a ; timer 1 overflow i_tim2c equ i_vec+$2c ; timer 2 compare i_tim2of equ i_vec+$2e ; timer 2 overflow ;--------------------------------------------------------------- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . b-16 dsp56309um/d motorola equates ; essi interrupts ;--------------------------------------------------------------- i_si0rd equ i_vec+$30 ; essi0 receive data i_si0rde equ i_vec+$32 ; essi0 receive data with exception status i_si0rls equ i_vec+$34 ; essi0 receive last slot i_si0td equ i_vec+$36 ; essi0 transmit data i_si0tde equ i_vec+$38 ; essi0 transmit data with exception status i_si0tls equ i_vec+$3a ; essi0 transmit last slot i_si1rd equ i_vec+$40 ; essi1 receive data i_si1rde equ i_vec+$42 ; essi1 receive data with exception status i_si1rls equ i_vec+$44 ; essi1 receive last slot i_si1td equ i_vec+$46 ; essi1 transmit data i_si1tde equ i_vec+$48 ; essi1 transmit data with exception status i_si1tls equ i_vec+$4a ; essi1 transmit last slot ;--------------------------------------------------------------- ; sci interrupts ;--------------------------------------------------------------- i_scird equ i_vec+$50 ; sci receive data i_scirde equ i_vec+$52 ; sci receive data with exception status i_scitd equ i_vec+$54 ; sci transmit data i_sciil equ i_vec+$56 ; sci idle line i_scitm equ i_vec+$58 ; sci timer ;--------------------------------------------------------------- ; host interrupts ;--------------------------------------------------------------- i_hrdf equ i_vec+$60 ; host receive data full i_htde equ i_vec+$62 ; host transmit data empty i_hc equ i_vec+$64 ; default host command ;--------------------------------------------------------------- ; interrupt ending address ;--------------------------------------------------------------- i_intend equ i_vec+$ff ; last address of interrupt vector space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d c-1 appendix c dsp56309 bsdl listing -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: mon apr 8 10:13:47 1996 -- -- revision history: -- entity dsp56303 is generic (physical_pin_map : string := "tqfp144"); port ( de_:inout bit; sc02:inout bit; sc01:inout bit; sc00:inout bit; std0:inout bit; sck0:inout bit; -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: mon apr 8 10:13:47 1996 -- -- revision history: -- entity dsp56309 is generic (physical_pin_map : string := "tqfp144"); port ( de_:inout bit; sc02:inout bit; sc01:inout bit; sc00:inout bit; std0:inout bit; sck0:inout bit; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-2 dsp56309um/d motorola dsp56309 bsdl listing -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: tue mar 3 15:14:41 1998 -- -- revision history: -- entity dsp56309 is generic (physical_pin_map : string := tqfp144); port ( de_n:inout bit; sc02:inout bit; sc01:inout bit; sc00:inout bit; std0:inout bit; sck0:inout bit; srd0:inout bit; srd1:inout bit; sck1:inout bit; std1:inout bit; sc10:inout bit; sc11:inout bit; sc12:inout bit; txd:inout bit; sclk:inout bit; rxd:inout bit; tio0:inout bit; tio1:inout bit; tio2:inout bit; had:inout bit_vector(0 to 7); hreq:inout bit; modd:in bit; modc:in bit; modb:in bit; moda:in bit; d:inout bit_vector(0 to 23); a:out bit_vector(0 to 17); extal:in bit; xtal:linkage bit; rd_n:out bit; wr_n:out bit; aa:out bit_vector(0 to 3); br_n:buffer bit; bg_n:in bit; bb_n:inout bit; pcap:linkage bit; reset_n:in bit; pinit:in bit; ta_n:in bit; cas_n:out bit; bclk:out bit; bclk_n:out bit; clkout:buffer bit; trst_n:in bit; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-3 tdo:out bit; tdi:in bit; tck:in bit; tms:in bit; reserved:linkage bit_vector(0 to 1); sgnd:linkage bit_vector(0 to 1); svcc:linkage bit_vector(0 to 1); qgnd:linkage bit_vector(0 to 3); qvcc:linkage bit_vector(0 to 3); hgnd:linkage bit; hvcc:linkage bit; dgnd:linkage bit_vector(0 to 3); dvcc:linkage bit_vector(0 to 3); agnd:linkage bit_vector(0 to 3); avcc:linkage bit_vector(0 to 3); jvcc:linkage bit; jgnd1:linkage bit; jgnd:linkage bit; hack:inout bit; hds:inout bit; hrw:inout bit; cvcc:linkage bit_vector(0 to 1); cgnd:linkage bit_vector(0 to 1); hcs:inout bit; ha9:inout bit; ha8:inout bit; has:inout bit); use std_1149_1_1994.all; attribute component_conformance of dsp56309 : entity is std_1149_1_1993; attribute pin_map of dsp56309 : entity is physical_pin_map; constant tqfp144 : pin_map_string := srd1: 1, & std1: 2, & sc02: 3, & sc01: 4, & de_n: 5, & pinit: 6, & srd0: 7, & svcc: (8, 25), & sgnd: (9, 26), & std0: 10, & sc10: 11, & sc00: 12, & rxd: 13, & txd: 14, & sclk: 15, & sck1: 16, & sck0: 17, & qvcc: (18, 56, 91, 126), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-4 dsp56309um/d motorola dsp56309 bsdl listing qgnd: (19, 54, 90, 127), & reserved: (49, 20), & hds: 21, & hrw: 22, & hack: 23, & hreq: 24, & tio2: 27, & tio1: 28, & tio0: 29, & hcs: 30, & ha9: 31, & ha8: 32, & has: 33, & had: (43, 42, 41, 40, 37, 36, 35, 34), & hvcc: 38, & hgnd: 39, & reset_n: 44, & jvcc: 45, & pcap: 46, & jgnd: 47, & jgnd1: 48, & aa: (70, 69, 51, 50), & cas_n: 52, & xtal: 53, & extal: 55, & cvcc: (57, 65), & cgnd: (58, 66), & clkout: 59, & bclk: 60, & bclk_n: 61, & ta_n: 62, & br_n: 63, & bb_n: 64, & wr_n: 67, & rd_n: 68, & bg_n: 71, & a: (72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), & avcc: (74, 80, 86, 95), & agnd: (75, 81, 87, 96), & d: (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, & 118, 121, 122, 123, 124, 125, 128, 131, 132, 133), & dvcc: (103, 111, 119, 129), & dgnd: (104, 112, 120, 130), & modd: 134, & modc: 135, & modb: 136, & moda: 137, & trst_n: 138, & tdo: 139, & tdi: 140, & tck: 141, & tms: 142, & sc12: 143, & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-5 sc11: 144 ; attribute tap_scan_in of tdi : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_reset of trst_n : signal is true; attribute tap_scan_clock of tck : signal is (20.0e6, both); attribute instruction_length of dsp56309 : entity is 4; attribute instruction_opcode of dsp56309 : entity is extest (0000), & sample (0001), & idcode (0010), & clamp (0101), & highz (0100), & enable_once (0110), & debug_request(0111), & bypass (1111); attribute instruction_capture of dsp56309 : entity is 0001; attribute idcode_register of dsp56309 : entity is 0010 & -- version 000110 & -- manufacturer?s use 0000000010 & -- sequence number 00000001110 & -- manufacturer identity 1; -- 1149.1 requirement attribute register_access of dsp56309 : entity is once[8] (enable_once,debug_request) ; attribute boundary_length of dsp56309 : entity is 144; attribute boundary_register of dsp56309 : entity is -- num cell port func safe [ccell dis rslt] 0 (bc_1, moda, input, x), & 1 (bc_1, modb, input, x), & 2 (bc_1, modc, input, x), & 3 (bc_1, modd, input, x), & 4 (bc_6, d(23), bidir, x, 13, 1, z), & 5 (bc_6, d(22), bidir, x, 13, 1, z), & 6 (bc_6, d(21), bidir, x, 13, 1, z), & 7 (bc_6, d(20), bidir, x, 13, 1, z), & 8 (bc_6, d(19), bidir, x, 13, 1, z), & 9 (bc_6, d(18), bidir, x, 13, 1, z), & 10 (bc_6, d(17), bidir, x, 13, 1, z), & 11 (bc_6, d(16), bidir, x, 13, 1, z), & 12 (bc_6, d(15), bidir, x, 13, 1, z), & 13 (bc_1, *, control, 1), & 14 (bc_6, d(14), bidir, x, 13, 1, z), & 15 (bc_6, d(13), bidir, x, 13, 1, z), & 16 (bc_6, d(12), bidir, x, 13, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-6 dsp56309um/d motorola dsp56309 bsdl listing 17 (bc_6, d(11), bidir, x, 26, 1, z), & 18 (bc_6, d(10), bidir, x, 26, 1, z), & 19 (bc_6, d(9), bidir, x, 26, 1, z), & -- num cell port func safe [ccell dis rslt] 20 (bc_6, d(8), bidir, x, 26, 1, z), & 21 (bc_6, d(7), bidir, x, 26, 1, z), & 22 (bc_6, d(6), bidir, x, 26, 1, z), & 23 (bc_6, d(5), bidir, x, 26, 1, z), & 24 (bc_6, d(4), bidir, x, 26, 1, z), & 25 (bc_6, d(3), bidir, x, 26, 1, z), & 26 (bc_1, *, control, 1), & 27 (bc_6, d(2), bidir, x, 26, 1, z), & 28 (bc_6, d(1), bidir, x, 26, 1, z), & 29 (bc_6, d(0), bidir, x, 26, 1, z), & 30 (bc_1, a(17), output3, x, 33, 1, z), & 31 (bc_1, a(16), output3, x, 33, 1, z), & 32 (bc_1, a(15), output3, x, 33, 1, z), & 33 (bc_1, *, control, 1), & 34 (bc_1, a(14), output3, x, 33, 1, z), & 35 (bc_1, a(13), output3, x, 33, 1, z), & 36 (bc_1, a(12), output3, x, 33, 1, z), & 37 (bc_1, a(11), output3, x, 33, 1, z), & 38 (bc_1, a(10), output3, x, 33, 1, z), & 39 (bc_1, a(9), output3, x, 33, 1, z), & -- num cell port func safe [ccell dis rslt] 40 (bc_1, a(8), output3, x, 43, 1, z), & 41 (bc_1, a(7), output3, x, 43, 1, z), & 42 (bc_1, a(6), output3, x, 43, 1, z), & 43 (bc_1, *, control, 1), & 44 (bc_1, a(5), output3, x, 43, 1, z), & 45 (bc_1, a(4), output3, x, 43, 1, z), & 46 (bc_1, a(3), output3, x, 43, 1, z), & 47 (bc_1, a(2), output3, x, 43, 1, z), & 48 (bc_1, a(1), output3, x, 43, 1, z), & 49 (bc_1, a(0), output3, x, 43, 1, z), & 50 (bc_1, bg_n, input, x), & 51 (bc_1, aa(0), output3, x, 55, 1, z), & 52 (bc_1, aa(1), output3, x, 56, 1, z), & 53 (bc_1, rd_n, output3, x, 64, 1, z), & 54 (bc_1, wr_n, output3, x, 64, 1, z), & 55 (bc_1, *, control, 1), & 56 (bc_1, *, control, 1), & 57 (bc_1, *, control, 1), & 58 (bc_6, bb_n, bidir, x, 57, 1, z), & 59 (bc_1, br_n, output2, x), & -- num cell port func safe [ccell dis rslt] 60 (bc_1, ta_n, input, x), & 61 (bc_1, bclk_n, output3, x, 64, 1, z), & 62 (bc_1, bclk, output3, x, 64, 1, z), & 63 (bc_1, clkout, output2, x), & 64 (bc_1, *, control, 1), & 65 (bc_1, *, control, 1), & 66 (bc_1, *, control, 1), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-7 67 (bc_1, *, control, 1), & 68 (bc_1, extal, input, x), & 69 (bc_1, cas_n, output3, x, 65, 1, z), & 70 (bc_1, aa(2), output3, x, 66, 1, z), & 71 (bc_1, aa(3), output3, x, 67, 1, z), & 72 (bc_1, reset_n, input, x), & 73 (bc_1, *, control, 1), & 74 (bc_6, had(0), bidir, x, 73, 1, z), & 75 (bc_1, *, control, 1), & 76 (bc_6, had(1), bidir, x, 75, 1, z), & 77 (bc_1, *, control, 1), & 78 (bc_6, had(2), bidir, x, 77, 1, z), & 79 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 80 (bc_6, had(3), bidir, x, 79, 1, z), & 81 (bc_1, *, control, 1), & 82 (bc_6, had(4), bidir, x, 81, 1, z), & 83 (bc_1, *, control, 1), & 84 (bc_6, had(5), bidir, x, 83, 1, z), & 85 (bc_1, *, control, 1), & 86 (bc_6, had(6), bidir, x, 85, 1, z), & 87 (bc_1, *, control, 1), & 88 (bc_6, had(7), bidir, x, 87, 1, z), & 89 (bc_1, *, control, 1), & 90 (bc_6, has, bidir, x, 89, 1, z), & 91 (bc_1, *, control, 1), & 92 (bc_6, ha8, bidir, x, 91, 1, z), & 93 (bc_1, *, control, 1), & 94 (bc_6, ha9, bidir, x, 93, 1, z), & 95 (bc_1, *, control, 1), & 96 (bc_6, hcs, bidir, x, 95, 1, z), & 97 (bc_1, *, control, 1), & 98 (bc_6, tio0, bidir, x, 97, 1, z), & 99 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 100 (bc_6, tio1, bidir, x, 99, 1, z), & 101 (bc_1, *, control, 1), & 102 (bc_6, tio2, bidir, x, 101, 1, z), & 103 (bc_1, *, control, 1), & 104 (bc_6, hreq, bidir, x, 103, 1, z), & 105 (bc_1, *, control, 1), & 106 (bc_6, hack, bidir, x, 105, 1, z), & 107 (bc_1, *, control, 1), & 108 (bc_6, hrw, bidir, x, 107, 1, z), & 109 (bc_1, *, control, 1), & 110 (bc_6, hds, bidir, x, 109, 1, z), & 111 (bc_1, *, control, 1), & 112 (bc_6, sck0, bidir, x, 111, 1, z), & 113 (bc_1, *, control, 1), & 114 (bc_6, sck1, bidir, x, 113, 1, z), & 115 (bc_1, *, control, 1), & 116 (bc_6, sclk, bidir, x, 115, 1, z), & 117 (bc_1, *, control, 1), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-8 dsp56309um/d motorola dsp56309 bsdl listing 118 (bc_6, txd, bidir, x, 117, 1, z), & 119 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 120 (bc_6, rxd, bidir, x, 119, 1, z), & 121 (bc_1, *, control, 1), & 122 (bc_6, sc00, bidir, x, 121, 1, z), & 123 (bc_1, *, control, 1), & 124 (bc_6, sc10, bidir, x, 123, 1, z), & 125 (bc_1, *, control, 1), & 126 (bc_6, std0, bidir, x, 125, 1, z), & 127 (bc_1, *, control, 1), & 128 (bc_6, srd0, bidir, x, 127, 1, z), & 129 (bc_1, pinit, input, x), & 130 (bc_1, *, control, 1), & 131 (bc_6, de_n, bidir, x, 130, 1, z), & 132 (bc_1, *, control, 1), & 133 (bc_6, sc01, bidir, x, 132, 1, z), & 134 (bc_1, *, control, 1), & 135 (bc_6, sc02, bidir, x, 134, 1, z), & 136 (bc_1, *, control, 1), & 137 (bc_6, std1, bidir, x, 136, 1, z), & 138 (bc_1, *, control, 1), & 139 (bc_6, srd1, bidir, x, 138, 1, z), & -- num cell port func safe [ccell dis rslt] 140 (bc_1, *, control, 1), & 141 (bc_6, sc11, bidir, x, 140, 1, z), & 142 (bc_1, *, control, 1), & 143 (bc_6, sc12, bidir, x, 142, 1, z); end dsp56309 tqfp; --------------------------------------------------------------------- -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: wed may 20 10:37:28 1998 -- -- revision history: -- -- 1) date : tue mar 3 15:14:41 1998 -- changes : created for dsp56309 rev0, pbga -- -- 2) date : wed may 20 10:37:28 1998 -- changes : fix in definition of de_n, it is pull1 when disabled -- updated by roman sajman -- entity dsp56309 is generic (physical_pin_map : string := tqfp144); port ( de_n: inout bit; sc02: inout bit; sc01: inout bit; sc00: inout bit; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-9 std0: inout bit; sck0: inout bit; srd0: inout bit; srd1: inout bit; sck1: inout bit; std1: inout bit; sc10: inout bit; sc11: inout bit; sc12: inout bit; txd: inout bit; sclk: inout bit; rxd: inout bit; tio0: inout bit; tio1: inout bit; tio2: inout bit; had: inout bit_vector(0 to 7); hreq: inout bit; modd: in bit; modc: in bit; modb: in bit; moda: in bit; d: inout bit_vector(0 to 23); a: out bit_vector(0 to 17); extal: in bit; xtal: linkage bit; rd_n: out bit; wr_n: out bit; aa: out bit_vector(0 to 3); br_n: buffer bit; bg_n: in bit; bb_n: inout bit; pcap: linkage bit; reset_n: in bit; pinit: in bit; ta_n: in bit; cas_n: out bit; bclk: out bit; bclk_n: out bit; clkout: buffer bit; trst_n: in bit; tdo: out bit; tdi: in bit; tck: in bit; tms: in bit; reserved: linkage bit_vector(0 to 1); sgnd: linkage bit_vector(0 to 1); svcc: linkage bit_vector(0 to 1); qgnd: linkage bit_vector(0 to 3); qvcc: linkage bit_vector(0 to 3); hgnd: linkage bit; hvcc: linkage bit; dgnd: linkage bit_vector(0 to 3); dvcc: linkage bit_vector(0 to 3); f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-10 dsp56309um/d motorola dsp56309 bsdl listing agnd: linkage bit_vector(0 to 3); avcc: linkage bit_vector(0 to 3); jvcc: linkage bit; jgnd1: linkage bit; jgnd: linkage bit; hack: inout bit; hds: inout bit; hrw: inout bit; cvcc: linkage bit_vector(0 to 1); cgnd: linkage bit_vector(0 to 1); hcs: inout bit; ha9: inout bit; ha8: inout bit; has: inout bit); use std_1149_1_1994.all; attribute component_conformance of dsp56309 : entity is std_1149_1_1993; attribute pin_map of dsp56309 : entity is physical_pin_map; constant tqfp144 : pin_map_string := srd1: 1, & std1: 2, & sc02: 3, & sc01: 4, & de_n: 5, & pinit: 6, & srd0: 7, & svcc: (8, 25), & sgnd: (9, 26), & std0: 10, & sc10: 11, & sc00: 12, & rxd: 13, & txd: 14, & sclk: 15, & sck1: 16, & sck0: 17, & qvcc: (18, 56, 91, 126), & qgnd: (19, 54, 90, 127), & reserved: (49, 20), & hds: 21, & hrw: 22, & hack: 23, & hreq: 24, & tio2: 27, & tio1: 28, & tio0: 29, & hcs: 30, & ha9: 31, & ha8: 32, & has: 33, & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-11 had: (43, 42, 41, 40, 37, 36, 35, 34), & hvcc: 38, & hgnd: 39, & reset_n: 44, & jvcc: 45, & pcap: 46, & jgnd: 47, & jgnd1: 48, & aa: (70, 69, 51, 50), & cas_n: 52, & xtal: 53, & extal: 55, & cvcc: (57, 65), & cgnd: (58, 66), & clkout: 59, & bclk: 60, & bclk_n: 61, & ta_n: 62, & br_n: 63, & bb_n: 64, & wr_n: 67, & rd_n: 68, & bg_n: 71, & a: (72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), & avcc: (74, 80, 86, 95), & agnd: (75, 81, 87, 96), & d: (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, 118, 121, & 122, 123, 124, 125, 128, 131, 132, 133), & dvcc: (103, 111, 119, 129), & dgnd: (104, 112, 120, 130), & modd: 134, & modc: 135, & modb: 136, & moda: 137, & trst_n: 138, & tdo: 139, & tdi: 140, & tck: 141, & tms: 142, & sc12: 143, & sc11: 144 ; attribute tap_scan_in of tdi : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_reset of trst_n : signal is true; attribute tap_scan_clock of tck : signal is (20.0e6, both); attribute instruction_length of dsp56309 : entity is 4; attribute instruction_opcode of dsp56309 : entity is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-12 dsp56309um/d motorola dsp56309 bsdl listing extest (0000), & sample (0001), & idcode (0010), & clamp (0101), & highz (0100), & enable_once (0110), & debug_request (0111), & bypass (1111); attribute instruction_capture of dsp56309 : entity is 0001; attribute idcode_register of dsp56309 : entity is 0010 & -- version 000110 & -- manufacturer?s use 0000000010 & -- sequence number 00000001110 & -- manufacturer identity 1; -- 1149.1 requirement attribute register_access of dsp56309 : entity is once[8] (enable_once,debug_request) ; attribute boundary_length of dsp56309 : entity is 144; attribute boundary_register of dsp56309 : entity is -- num cell port func safe [ccell dis rslt] 0 (bc_1, moda, input, x), & 1 (bc_1, modb, input, x), & 2 (bc_1, modc, input, x), & 3 (bc_1, modd, input, x), & 4 (bc_6, d(23), bidir, x, 13, 1, z), & 5 (bc_6, d(22), bidir, x, 13, 1, z), & 6 (bc_6, d(21), bidir, x, 13, 1, z), & 7 (bc_6, d(20), bidir, x, 13, 1, z), & 8 (bc_6, d(19), bidir, x, 13, 1, z), & 9 (bc_6, d(18), bidir, x, 13, 1, z), & 10 (bc_6, d(17), bidir, x, 13, 1, z), & 11 (bc_6, d(16), bidir, x, 13, 1, z), & 12 (bc_6, d(15), bidir, x, 13, 1, z), & 13 (bc_1, *, control, 1), & 14 (bc_6, d(14), bidir, x, 13, 1, z), & 15 (bc_6, d(13), bidir, x, 13, 1, z), & 16 (bc_6, d(12), bidir, x, 13, 1, z), & 17 (bc_6, d(11), bidir, x, 26, 1, z), & 18 (bc_6, d(10), bidir, x, 26, 1, z), & 19 (bc_6, d(9), bidir, x, 26, 1, z), & -- num cell port func safe [ccell dis rslt] 20 (bc_6, d(8), bidir, x, 26, 1, z), & 21 (bc_6, d(7), bidir, x, 26, 1, z), & 22 (bc_6, d(6), bidir, x, 26, 1, z), & 23 (bc_6, d(5), bidir, x, 26, 1, z), & 24 (bc_6, d(4), bidir, x, 26, 1, z), & 25 (bc_6, d(3), bidir, x, 26, 1, z), & 26 (bc_1, *, control, 1), & 27 (bc_6, d(2), bidir, x, 26, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-13 28 (bc_6, d(1), bidir, x, 26, 1, z), & 29 (bc_6, d(0), bidir, x, 26, 1, z), & 30 (bc_1, a(17), output3, x, 33, 1, z), & 31 (bc_1, a(16), output3, x, 33, 1, z), & 32 (bc_1, a(15), output3, x, 33, 1, z), & 33 (bc_1, *, control, 1), & 34 (bc_1, a(14), output3, x, 33, 1, z), & 35 (bc_1, a(13), output3, x, 33, 1, z), & 36 (bc_1, a(12), output3, x, 33, 1, z), & 37 (bc_1, a(11), output3, x, 33, 1, z), & 38 (bc_1, a(10), output3, x, 33, 1, z), & 39 (bc_1, a(9), output3, x, 33, 1, z), & -- num cell port func safe [ccell dis rslt] 40 (bc_1, a(8), output3, x, 43, 1, z), & 41 (bc_1, a(7), output3, x, 43, 1, z), & 42 (bc_1, a(6), output3, x, 43, 1, z), & 43 (bc_1, *, control, 1), & 44 (bc_1, a(5), output3, x, 43, 1, z), & 45 (bc_1, a(4), output3, x, 43, 1, z), & 46 (bc_1, a(3), output3, x, 43, 1, z), & 47 (bc_1, a(2), output3, x, 43, 1, z), & 48 (bc_1, a(1), output3, x, 43, 1, z), & 49 (bc_1, a(0), output3, x, 43, 1, z), & 50 (bc_1, bg_n, input, x), & 51 (bc_1, aa(0), output3, x, 55, 1, z), & 52 (bc_1, aa(1), output3, x, 56, 1, z), & 53 (bc_1, rd_n, output3, x, 64, 1, z), & 54 (bc_1, wr_n, output3, x, 64, 1, z), & 55 (bc_1, *, control, 1), & 56 (bc_1, *, control, 1), & 57 (bc_1, *, control, 1), & 58 (bc_6, bb_n, bidir, x, 57, 1, z), & 59 (bc_1, br_n, output2, x), & -- num cell port func safe [ccell dis rslt] 60 (bc_1, ta_n, input, x), & 61 (bc_1, bclk_n, output3, x, 64, 1, z), & 62 (bc_1, bclk, output3, x, 64, 1, z), & 63 (bc_1, clkout, output2, x), & 64 (bc_1, *, control, 1), & 65 (bc_1, *, control, 1), & 66 (bc_1, *, control, 1), & 67 (bc_1, *, control, 1), & 68 (bc_1, extal, input, x), & 69 (bc_1, cas_n, output3, x, 65, 1, z), & 70 (bc_1, aa(2), output3, x, 66, 1, z), & 71 (bc_1, aa(3), output3, x, 67, 1, z), & 72 (bc_1, reset_n, input, x), & 73 (bc_1, *, control, 1), & 74 (bc_6, had(0), bidir, x, 73, 1, z), & 75 (bc_1, *, control, 1), & 76 (bc_6, had(1), bidir, x, 75, 1, z), & 77 (bc_1, *, control, 1), & 78 (bc_6, had(2), bidir, x, 77, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-14 dsp56309um/d motorola dsp56309 bsdl listing 79 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 80 (bc_6, had(3), bidir, x, 79, 1, z), & 81 (bc_1, *, control, 1), & 82 (bc_6, had(4), bidir, x, 81, 1, z), & 83 (bc_1, *, control, 1), & 84 (bc_6, had(5), bidir, x, 83, 1, z), & 85 (bc_1, *, control, 1), & 86 (bc_6, had(6), bidir, x, 85, 1, z), & 87 (bc_1, *, control, 1), & 88 (bc_6, had(7), bidir, x, 87, 1, z), & 89 (bc_1, *, control, 1), & 90 (bc_6, has, bidir, x, 89, 1, z), & 91 (bc_1, *, control, 1), & 92 (bc_6, ha8, bidir, x, 91, 1, z), & 93 (bc_1, *, control, 1), & 94 (bc_6, ha9, bidir, x, 93, 1, z), & 95 (bc_1, *, control, 1), & 96 (bc_6, hcs, bidir, x, 95, 1, z), & 97 (bc_1, *, control, 1), & 98 (bc_6, tio0, bidir, x, 97, 1, z), & 99 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 100 (bc_6, tio1, bidir, x, 99, 1, z), & 101 (bc_1, *, control, 1), & 102 (bc_6, tio2, bidir, x, 101, 1, z), & 103 (bc_1, *, control, 1), & 104 (bc_6, hreq, bidir, x, 103, 1, z), & 105 (bc_1, *, control, 1), & 106 (bc_6, hack, bidir, x, 105, 1, z), & 107 (bc_1, *, control, 1), & 108 (bc_6, hrw, bidir, x, 107, 1, z), & 109 (bc_1, *, control, 1), & 110 (bc_6, hds, bidir, x, 109, 1, z), & 111 (bc_1, *, control, 1), & 112 (bc_6, sck0, bidir, x, 111, 1, z), & 113 (bc_1, *, control, 1), & 114 (bc_6, sck1, bidir, x, 113, 1, z), & 115 (bc_1, *, control, 1), & 116 (bc_6, sclk, bidir, x, 115, 1, z), & 117 (bc_1, *, control, 1), & 118 (bc_6, txd, bidir, x, 117, 1, z), & 119 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 120 (bc_6, rxd, bidir, x, 119, 1, z), & 121 (bc_1, *, control, 1), & 122 (bc_6, sc00, bidir, x, 121, 1, z), & 123 (bc_1, *, control, 1), & 124 (bc_6, sc10, bidir, x, 123, 1, z), & 125 (bc_1, *, control, 1), & 126 (bc_6, std0, bidir, x, 125, 1, z), & 127 (bc_1, *, control, 1), & 128 (bc_6, srd0, bidir, x, 127, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-15 129 (bc_1, pinit, input, x), & 130 (bc_1, *, control, 1), & 131 (bc_6, de_n, bidir, x, 130, 1, pull1), & 132 (bc_1, *, control, 1), & 133 (bc_6, sc01, bidir, x, 132, 1, z), & 134 (bc_1, *, control, 1), & 135 (bc_6, sc02, bidir, x, 134, 1, z), & 136 (bc_1, *, control, 1), & 137 (bc_6, std1, bidir, x, 136, 1, z), & 138 (bc_1, *, control, 1), & 139 (bc_6, srd1, bidir, x, 138, 1, z), & -- num cell port func safe [ccell dis rslt] 140 (bc_1, *, control, 1), & 141 (bc_6, sc11, bidir, x, 140, 1, z), & 142 (bc_1, *, control, 1), & 143 (bc_6, sc12, bidir, x, 142, 1, z); end dsp56309; --------------------------------------------------------------------- -- m o t o r o l a s s d t j t a g s o f t w a r e -- bsdl file generated: wed may 20 09:48:32 1998 -- -- revision history: -- entity dsp56309 is generic (physical_pin_map : string := pbga196); port ( de_n: inout bit; sc02: inout bit; sc01: inout bit; sc00: inout bit; std0: inout bit; sck0: inout bit; srd0: inout bit; srd1: inout bit; sck1: inout bit; std1: inout bit; sc10: inout bit; sc11: inout bit; sc12: inout bit; txd: inout bit; sclk: inout bit; rxd: inout bit; tio0: inout bit; tio1: inout bit; tio2: inout bit; had: inout bit_vector(0 to 7); hreq: inout bit; modd: in bit; modc: in bit; modb: in bit; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-16 dsp56309um/d motorola dsp56309 bsdl listing moda: in bit; d: inout bit_vector(0 to 23); a: out bit_vector(0 to 17); extal: in bit; xtal: linkage bit; rd_n: out bit; wr_n: out bit; aa: out bit_vector(0 to 3); br_n: buffer bit; bg_n: in bit; bb_n: inout bit; pcap: linkage bit; reset_n: in bit; pinit: in bit; ta_n: in bit; cas_n: out bit; bclk: out bit; bclk_n: out bit; clkout: buffer bit; trst_n: in bit; tdo: out bit; tdi: in bit; tck: in bit; tms: in bit; reserved: linkage bit_vector(0 to 4); svcc: linkage bit_vector(0 to 1); hvcc: linkage bit; dvcc: linkage bit_vector(0 to 3); avcc: linkage bit_vector(0 to 2); hack: inout bit; hds: inout bit; hrw: inout bit; cvcc: linkage bit_vector(0 to 1); hcs: inout bit; ha9: inout bit; ha8: inout bit; has: inout bit; gnd: linkage bit_vector(0 to 63); qvccl: linkage bit_vector(0 to 3); qvcch: linkage bit_vector(0 to 2); pvcc: linkage bit; pgnd: linkage bit; pgnd1: linkage bit); use std_1149_1_1994.all; attribute component_conformance of dsp56309 : entity is std_1149_1_1993; attribute pin_map of dsp56309 : entity is physical_pin_map; constant pbga196 : pin_map_string := reserved: (a1, a14, b14, p1, p14), & sc11: a2, & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-17 tms: a3, & tdo: a4, & modb: a5, & d: (e14, d12, d13, c13, c14, b13, c12, a13, b12, a12, b11, a11, c10, b10, a10, b9, & a9, b8, c8, a8, b7, b6, c6, a6), & dvcc: (a7, c9, c11, d14), & srd1: b1, & sc12: b2, & tdi: b3, & trst_n: b4, & modd: b5, & sc02: c1, & std1: c2, & tck: c3, & moda: c4, & modc: c5, & qvccl: (c7, g13, h2, n9), & pinit: d1, & sc01: d2, & de_n: d3, & gnd: (e8, e9, e10, e11, f4, f5, f11, g4, g5, g6, g7, g8, g9, g10, g11, h4, h5, h6, & h7, h8, h9, h10, h11, j4, j5, j6, j7, j8, j9, j10, j11, k4, k5, k6, k7, k8, k9, & k10, k11, l4, l5, l6, l7, l8, l9, l10, l11, d4, d5, d6, d7, d8, d9, d10, d11, e4, & e5, e6, e7, f6, f7, f8, f9, f10), & std0: e1, & svcc: (e2, k1), & srd0: e3, & a: (n14, m13, m14, l13, l14, k13, k14, j13, j12, j14, h13, h14, g14, g12, f13, f14, & e13, e12), & rxd: f1, & sc10: f2, & sc00: f3, & qvcch: (f12, h1, m7), & sck1: g1, & sclk: g2, & txd: g3, & sck0: h3, & avcc: (h12, k12, l12), & hack: j1, & hrw: j2, & hds: j3, & hreq: k2, & tio2: k3, & hcs: l1, & tio1: l2, & tio0: l3, & ha8: m1, & ha9: m2, & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-18 dsp56309um/d motorola dsp56309 bsdl listing has: m3, & hvcc: m4, & had: (m5, p4, n4, p3, n3, p2, n1, n2), & pvcc: m6, & extal: m8, & clkout: m9, & bclk_n: m10, & wr_n: m11, & rd_n: m12, & reset_n: n5, & pgnd: n6, & aa: (n13, p12, p7, n7), & cas_n: n8, & bclk: n10, & br_n: n11, & cvcc: (n12, p9), & pcap: p5, & pgnd1: p6, & xtal: p8, & ta_n: p10, & bb_n: p11, & bg_n: p13 ; attribute tap_scan_in of tdi : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_reset of trst_n : signal is true; attribute tap_scan_clock of tck : signal is (20.0e6, both); attribute instruction_length of dsp56309 : entity is 4; attribute instruction_opcode of dsp56309 : entity is extest (0000), & sample (0001), & idcode (0010), & clamp (0101), & highz (0100), & enable_once (0110), & debug_request (0111), & bypass (1111); attribute instruction_capture of dsp56309 : entity is 0001; attribute idcode_register of dsp56309 : entity is 0010 & -- version 000110 & -- manufacturer?s use 0000000010 & -- sequence number 00000001110 & -- manufacturer identity 1; -- 1149.1 requirement attribute register_access of dsp56309 : entity is once[8] (enable_once,debug_request) ; attribute boundary_length of dsp56309 : entity is 144; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-19 attribute boundary_register of dsp56309 : entity is -- num cell port func safe [ccell dis rslt] 0 (bc_1, moda, input, x), & 1 (bc_1, modb, input, x), & 2 (bc_1, modc, input, x), & 3 (bc_1, modd, input, x), & 4 (bc_6, d(23), bidir, x, 13, 1, z), & 5 (bc_6, d(22), bidir, x, 13, 1, z), & 6 (bc_6, d(21), bidir, x, 13, 1, z), & 7 (bc_6, d(20), bidir, x, 13, 1, z), & 8 (bc_6, d(19), bidir, x, 13, 1, z), & 9 (bc_6, d(18), bidir, x, 13, 1, z), & 10 (bc_6, d(17), bidir, x, 13, 1, z), & 11 (bc_6, d(16), bidir, x, 13, 1, z), & 12 (bc_6, d(15), bidir, x, 13, 1, z), & 13 (bc_1, *, control, 1), & 14 (bc_6, d(14), bidir, x, 13, 1, z), & 15 (bc_6, d(13), bidir, x, 13, 1, z), & 16 (bc_6, d(12), bidir, x, 13, 1, z), & 17 (bc_6, d(11), bidir, x, 26, 1, z), & 18 (bc_6, d(10), bidir, x, 26, 1, z), & 19 (bc_6, d(9), bidir, x, 26, 1, z), & -- num cell port func safe [ccell dis rslt] 20 (bc_6, d(8), bidir, x, 26, 1, z), & 21 (bc_6, d(7), bidir, x, 26, 1, z), & 22 (bc_6, d(6), bidir, x, 26, 1, z), & 23 (bc_6, d(5), bidir, x, 26, 1, z), & 24 (bc_6, d(4), bidir, x, 26, 1, z), & 25 (bc_6, d(3), bidir, x, 26, 1, z), & 26 (bc_1, *, control, 1), & 27 (bc_6, d(2), bidir, x, 26, 1, z), & 28 (bc_6, d(1), bidir, x, 26, 1, z), & 29 (bc_6, d(0), bidir, x, 26, 1, z), & 30 (bc_1, a(17), output3, x, 33, 1, z), & 31 (bc_1, a(16), output3, x, 33, 1, z), & 32 (bc_1, a(15), output3, x, 33, 1, z), & 33 (bc_1, *, control, 1), & 34 (bc_1, a(14), output3, x, 33, 1, z), & 35 (bc_1, a(13), output3, x, 33, 1, z), & 36 (bc_1, a(12), output3, x, 33, 1, z), & 37 (bc_1, a(11), output3, x, 33, 1, z), & 38 (bc_1, a(10), output3, x, 33, 1, z), & 39 (bc_1, a(9), output3, x, 33, 1, z), & -- num cell port func safe [ccell dis rslt] 40 (bc_1, a(8), output3, x, 43, 1, z), & 41 (bc_1, a(7), output3, x, 43, 1, z), & 42 (bc_1, a(6), output3, x, 43, 1, z), & 43 (bc_1, *, control, 1), & 44 (bc_1, a(5), output3, x, 43, 1, z), & 45 (bc_1, a(4), output3, x, 43, 1, z), & 46 (bc_1, a(3), output3, x, 43, 1, z), & 47 (bc_1, a(2), output3, x, 43, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-20 dsp56309um/d motorola dsp56309 bsdl listing 48 (bc_1, a(1), output3, x, 43, 1, z), & 49 (bc_1, a(0), output3, x, 43, 1, z), & 50 (bc_1, bg_n, input, x), & 51 (bc_1, aa(0), output3, x, 55, 1, z), & 52 (bc_1, aa(1), output3, x, 56, 1, z), & 53 (bc_1, rd_n, output3, x, 64, 1, z), & 54 (bc_1, wr_n, output3, x, 64, 1, z), & 55 (bc_1, *, control, 1), & 56 (bc_1, *, control, 1), & 57 (bc_1, *, control, 1), & 58 (bc_6, bb_n, bidir, x, 57, 1, z), & 59 (bc_1, br_n, output2, x), & -- num cell port func safe [ccell dis rslt] 60 (bc_1, ta_n, input, x), & 61 (bc_1, bclk_n, output3, x, 64, 1, z), & 62 (bc_1, bclk, output3, x, 64, 1, z), & 63 (bc_1, clkout, output2, x), & 64 (bc_1, *, control, 1), & 65 (bc_1, *, control, 1), & 66 (bc_1, *, control, 1), & 67 (bc_1, *, control, 1), & 68 (bc_1, extal, input, x), & 69 (bc_1, cas_n, output3, x, 65, 1, z), & 70 (bc_1, aa(2), output3, x, 66, 1, z), & 71 (bc_1, aa(3), output3, x, 67, 1, z), & 72 (bc_1, reset_n, input, x), & 73 (bc_1, *, control, 1), & 74 (bc_6, had(0), bidir, x, 73, 1, z), & 75 (bc_1, *, control, 1), & 76 (bc_6, had(1), bidir, x, 75, 1, z), & 77 (bc_1, *, control, 1), & 78 (bc_6, had(2), bidir, x, 77, 1, z), & 79 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 80 (bc_6, had(3), bidir, x, 79, 1, z), & 81 (bc_1, *, control, 1), & 82 (bc_6, had(4), bidir, x, 81, 1, z), & 83 (bc_1, *, control, 1), & 84 (bc_6, had(5), bidir, x, 83, 1, z), & 85 (bc_1, *, control, 1), & 86 (bc_6, had(6), bidir, x, 85, 1, z), & 87 (bc_1, *, control, 1), & 88 (bc_6, had(7), bidir, x, 87, 1, z), & 89 (bc_1, *, control, 1), & 90 (bc_6, has, bidir, x, 89, 1, z), & 91 (bc_1, *, control, 1), & 92 (bc_6, ha8, bidir, x, 91, 1, z), & 93 (bc_1, *, control, 1), & 94 (bc_6, ha9, bidir, x, 93, 1, z), & 95 (bc_1, *, control, 1), & 96 (bc_6, hcs, bidir, x, 95, 1, z), & 97 (bc_1, *, control, 1), & 98 (bc_6, tio0, bidir, x, 97, 1, z), & f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56309 bsdl listing motorola dsp56309um/d c-21 99 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 100 (bc_6, tio1, bidir, x, 99, 1, z), & 101 (bc_1, *, control, 1), & 102 (bc_6, tio2, bidir, x, 101, 1, z), & 103 (bc_1, *, control, 1), & 104 (bc_6, hreq, bidir, x, 103, 1, z), & 105 (bc_1, *, control, 1), & 106 (bc_6, hack, bidir, x, 105, 1, z), & 107 (bc_1, *, control, 1), & 108 (bc_6, hrw, bidir, x, 107, 1, z), & 109 (bc_1, *, control, 1), & 110 (bc_6, hds, bidir, x, 109, 1, z), & 111 (bc_1, *, control, 1), & 112 (bc_6, sck0, bidir, x, 111, 1, z), & 113 (bc_1, *, control, 1), & 114 (bc_6, sck1, bidir, x, 113, 1, z), & 115 (bc_1, *, control, 1), & 116 (bc_6, sclk, bidir, x, 115, 1, z), & 117 (bc_1, *, control, 1), & 118 (bc_6, txd, bidir, x, 117, 1, z), & 119 (bc_1, *, control, 1), & -- num cell port func safe [ccell dis rslt] 120 (bc_6, rxd, bidir, x, 119, 1, z), & 121 (bc_1, *, control, 1), & 122 (bc_6, sc00, bidir, x, 121, 1, z), & 123 (bc_1, *, control, 1), & 124 (bc_6, sc10, bidir, x, 123, 1, z), & 125 (bc_1, *, control, 1), & 126 (bc_6, std0, bidir, x, 125, 1, z), & 127 (bc_1, *, control, 1), & 128 (bc_6, srd0, bidir, x, 127, 1, z), & 129 (bc_1, pinit, input, x), & 130 (bc_1, *, control, 1), & 131 (bc_6, de_n, bidir, x, 130, 1, pull1), & 132 (bc_1, *, control, 1), & 133 (bc_6, sc01, bidir, x, 132, 1, z), & 134 (bc_1, *, control, 1), & 135 (bc_6, sc02, bidir, x, 134, 1, z), & 136 (bc_1, *, control, 1), & 137 (bc_6, std1, bidir, x, 136, 1, z), & 138 (bc_1, *, control, 1), & 139 (bc_6, srd1, bidir, x, 138, 1, z), & -- num cell port func safe [ccell dis rslt] 140 (bc_1, *, control, 1), & 141 (bc_6, sc11, bidir, x, 140, 1, z), & 142 (bc_1, *, control, 1), & 143 (bc_6, sc12, bidir, x, 142, 1, z); end dsp56309; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . c-22 dsp56309um/d motorola dsp56309 bsdl listing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d d-1 appendix d programming reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-2 dsp56309um/d motorola programming reference d.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 d.2 internal i/o memory map . . . . . . . . . . . . . . . . . . . . . . . d-4 d.3 interrupt addresses and sources . . . . . . . . . . . d-11 d.4 interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . d-13 d.5 programming reference: central processor . . . . . . . . . . . . . . . . . . . . . . . . . . d-15 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-19 host interface (hi08) . . . . . . . . . . . . . . . . . . . . . . . . . d-20 enhanced synchronous serial interface (essi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-26 serial communications interface . . . . . . . . . . . . d-30 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-33 general purpose i/o (gpio). . . . . . . . . . . . . . . . . . . . d-36 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-3 d.1 introduction this section has been compiled as a reference for programmers. it contains a table showing the addresses of all the dsp?s memory-mapped peripherals, an exception priority table, and programming sheets for the major programmable registers on the dsp. the programming sheets are grouped in the following order: central processor, phase-locked loop (pll), host interface (hi08), enhanced synchronous serial interface (essi), serial communication interface (sci), timer, and gpio. each sheet provides room to write in the value of each bit and the hexadecimal value for each register. the programmer can photocopy these sheets and reuse them for each application development project. for details about the instruction set of the dsp56300 family chips, see the dsp56300 family manual . d.1.1 peripheral addresses table d-1 lists the memory addresses of all on-chip peripherals. d.1.2 interrupt addresses table d-2 on page -11 lists the interrupt starting addresses and sources. d.1.3 interrupt priorities table d-3 on page -13 lists the priorities of specific interrupts within interrupt priority levels. d.1.4 programming sheets the remaining figures show the major programmable registers on the dsp56309. peripheral addresses f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-4 dsp56309um/d motorola programming reference d.2 internal i/o memory map table d-1 internal i/o memory map peripheral 16-bit address 24-bit address register name ipr $ffff $ffffff interrupt priority register core (ipr-c) $fffe $fffffe interrupt priority register peripheral (ipr-p) pll $fffd $fffffd pll control register (pctl) once $fffc $fffffc once gdb register (ogdb) biu $fffb $fffffb bus control register (bcr) $fffa $fffffa dram control register (dcr) $fff9 $fffff9 address attribute register 0 (aar0) $fff8 $fffff8 address attribute register 1 (aar1) $fff7 $fffff7 address attribute register 2 (aar2) $fff6 $fffff6 address attribute register 3 (aar3) $fff5 $fffff5 id register (idr) dma $fff4 $fffff4 dma status register (dstr) $fff3 $fffff3 dma offset register 0 (dor0) $fff2 $fffff2 dma offset register 1 (dor1) $fff1 $fffff1 dma offset register 2 (dor2) $fff0 $fffff0 dma offset register 3 (dor3) dma0 $ffef $ffffef dma source address register (dsr0) $ffee $ffffee dma destination address register (ddr0) $ffed $ffffed dma counter (dco0) $ffec $ffffec dma control register (dcr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-5 dma1 $ffeb $ffffeb dma source address register (dsr1) $ffea $ffffea dma destination address register (ddr1) $ffe9 $ffffe9 dma counter (dco1) $ffe8 $ffffe8 dma control register (dcr1) dma2 $ffe7 $ffffe7 dma source address register (dsr2) $ffe6 $ffffe6 dma destination address register (ddr2) $ffe5 $ffffe5 dma counter (dco2) $ffe4 $ffffe4 dma control register (dcr2) dma3 $ffe3 $ffffe3 dma source address register (dsr3) $ffe2 $ffffe2 dma destination address register (ddr3) $ffe1 $ffffe1 dma counter (dco3) $ffe0 $ffffe0 dma control register (dcr3) dma4 $ffdf $ffffdf dma source address register (dsr4) $ffde $ffffde dma destination address register (ddr4) $ffdd $ffffdd dma counter (dco4) $ffdc $ffffdc dma control register (dcr4) dma5 $ffdb $ffffdb dma source address register (dsr5) $ffda $ffffda dma destination address register (ddr5) $ffd9 $ffffd9 dma counter (dco5) $ffd8 $ffffd8 dma control register (dcr5) table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-6 dsp56309um/d motorola programming reference ? $ffd7 $ffffd7 reserved $ffd6 $ffffd6 reserved $ffd5 $ffffd5 reserved $ffd4 $ffffd4 reserved $ffd3 $ffffd3 reserved $ffd2 $ffffd2 reserved $ffd1 $ffffd1 reserved $ffd0 $ffffd0 reserved ? $ffcf $ffffcf reserved $ffce $ffffce reserved $ffcd $ffffcd reserved $ffcc $ffffcc reserved $ffcb $ffffcb reserved $ffca $ffffca reserved port b $ffc9 $ffffc9 host port gpio data register (hdr) $ffc8 $ffffc8 host port gpio direction register (hddr) hi08 $ffc7 $ffffc7 host transmit register (htx) $ffc6 $ffffc6 host receive register (hrx) $ffc5 $ffffc5 host base address register (hbar) $ffc4 $ffffc4 host polarity control register (hpcr) $ffc3 $ffffc3 host status register (hsr) $ffc2 $ffffc2 host control register (hcr) $ffc1 $ffffc1 reserved $ffc0 $ffffc0 reserved table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-7 port c $ffbf $ffffbf port c control register (pcrc) $ffbe $ffffbe port c direction register (prrc) $ffbd $ffffbd port c gpio data register (pdrc) essi 0 $ffbc $ffffbc essi 0 transmit data register 0 (tx00) $ffbb $ffffbb essi 0 transmit data register 1 (tx01) $ffba $ffffba essi 0 transmit data register 2 (tx02) $ffb9 $ffffb9 essi 0 time slot register (tsr0) $ffb8 $ffffb8 essi 0 receive data register (rx0) $ffb7 $ffffb7 essi 0 status register (ssisr0) $ffb6 $ffffb6 essi 0 control register b (crb0) $ffb5 $ffffb5 essi 0 control register a (cra0) $ffb4 $ffffb4 essi 0 transmit slot mask register a (tsma0) $ffb3 $ffffb3 essi 0 transmit slot mask register b (tsmb0) $ffb2 $ffffb2 essi 0 receive slot mask register a (rsma0) $ffb1 $ffffb1 essi 0 receive slot mask register b (rsmb0) ? $ffb0 $ffffb0 reserved port d $ffaf $ffffaf port d control register (pcrd) $ffae $ffffae port d direction register (prrd) $ffad $ffffad port c gpio data register (pdrd) table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-8 dsp56309um/d motorola programming reference essi 1 $ffac $ffffac essi 1 transmit data register 0 (tx10) $ffab $ffffab essi 1 transmit data register 1 (tx11) $ffaa $ffffaa essi 1 transmit data register 2 (tx12) $ffa9 $ffffa9 essi 1 time slot register (tsr1) $ffa8 $ffffa8 essi 1 receive data register (rx1) $ffa7 $ffffa7 essi 1 status register (ssisr1) $ffa6 $ffffa6 essi 1 control register b (crb1) $ffa5 $ffffa5 essi 1 control register a (cra1) $ffa4 $ffffa4 essi 1 transmit slot mask register a (tsma1) $ffa3 $ffffa3 essi 1 transmit slot mask register b (tsmb1) $ffa2 $ffffa2 essi 1 receive slot mask register a (rsma1) $ffa1 $ffffa1 essi 1 receive slot mask register b (rsmb1) ? $ffa0 $ffffa0 reserved port e $ff9f $ffff9f port e control register (pcre) $ff9e $ffff9e port e direction register (prre) $ff9d $ffff9d port e gpio data register (pdre) table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-9 sci $ff9c $ffff9c sci control register (scr) $ff9b $ffff9b sci clock control register (sccr) $ff9a $ffff9a sci receive data register - high (srxh) $ff99 $ffff99 sci receive data register - middle (srxm) $ff98 $ffff98 sci recieve data register - low (srxl) $ff97 $ffff97 sci transmit data register - high (stxh) $ff96 $ffff96 sci transmit data register - middle (stxm) $ff95 $ffff95 sci transmit data register - low (stxl) $ff94 $ffff94 sci transmit address register (stxa) $ff93 $ffff93 sci status register (ssr) ? $ff92 $ffff92 reserved $ff91 $ffff91 reserved $ff90 $ffff90 reserved table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-10 dsp56309um/d motorola programming reference triple timer $ff8f $ffff8f timer 0 control/status register (tcsr0) $ff8e $ffff8e timer 0 load register (tlr0) $ff8d $ffff8d timer 0 compare register (tcpr0) $ff8c $ffff8c timer 0 count register (tcr0) $ff8b $ffff8b timer 1 control/status register (tcsr1) $ff8a $ffff8a timer 1 load register (tlr1) $ff89 $ffff89 timer 1 compare register (tcpr1) $ff88 $ffff88 timer 1 count register (tcr1) $ff87 $ffff87 timer 2 control/status register (tcsr2) $ff86 $ffff86 timer 2 load register (tlr2) $ff85 $ffff85 timer 2 compare register (tcpr2) $ff84 $ffff84 timer 2 count register (tcr2) $ff83 $ffff83 timer prescaler load register (tplr) $ff82 $ffff82 timer prescaler count register (tpcr) ? $ff81 $ffff81 reserved $ff80 $ffff80 reserved table d-1 internal i/o memory map (continued) peripheral 16-bit address 24-bit address register name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-11 d.3 interrupt addresses and sources table d-2 interrupt sources interrupt starting address interrupt priority level range interrupt source vba:$00 3 hardware reset vba:$02 3 stack error vba:$04 3 illegal instruction vba:$06 3 debug request interrupt vba:$08 3 trap vba:$0a 3 non-maskable interrupt (nmi ) vba:$0c 3 reserved vba:$0e 3 reserved vba:$10 0e2 irqa vba:$12 0e2 irqb vba:$14 0e2 irqc vba:$16 0e2 irqd vba:$18 0e2 dma channel 0 vba:$1a 0e2 dma channel 1 vba:$1c 0e2 dma channel 2 vba:$1e 0e2 dma channel 3 vba:$20 0e2 dma channel 4 vba:$22 0e2 dma channel 5 vba:$24 0e2 timer 0 compare vba:$26 0e2 timer 0 overflow vba:$28 0e2 timer 1 compare vba:$2a 0e2 timer 1 overflow vba:$2c 0e2 timer 2 compare vba:$2e 0e2 timer 2 overflow vba:$30 0e2 essi0 receive data vba:$32 0e2 essi0 receive data with exception status vba:$34 0e2 essi0 receive last slot vba:$36 0e2 essi0 transmit data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-12 dsp56309um/d motorola programming reference vba:$38 0e2 essi0 transmit data with exception status vba:$3a 0e2 essi0 transmit last slot vba:$3c 0e2 reserved vba:$3e 0e2 reserved vba:$40 0e2 essi1 receive data vba:$42 0e2 essi1 receive data with exception status vba:$44 0e2 essi1 receive last slot vba:$46 0e2 essi1 transmit data vba:$48 0e2 essi1 transmit data with exception status vba:$4a 0e2 essi1 transmit last slot vba:$4c 0e2 reserved vba:$4e 0e2 reserved vba:$50 0e2 sci receive data vba:$52 0e2 sci receive data with exception status vba:$54 0e2 sci transmit data vba:$56 0e2 sci idle line vba:$58 0e2 sci timer vba:$5a 0e2 reserved vba:$5c 0e2 reserved vba:$5e 0e2 reserved vba:$60 0e2 host receive data full vba:$62 0e2 host transmit data empty vba:$64 0e2 host command (default) vba:$66 0e2 reserved ::: vba:$fe 0e2 reserved table d-2 interrupt sources (continued) interrupt starting address interrupt priority level range interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-13 d.4 interrupt priorities table d-3 interrupt source priorities within an ipl priority interrupt source level 3 (nonmaskable) highest hardware reset ? stack error ? illegal instruction ? debug request interrupt ? trap lowest non-maskable interrupt levels 0, 1, 2 (maskable) highest irqa (external interrupt) ? irqb (external interrupt) ? irqc (external interrupt) ? irqd (external interrupt) ? dma channel 0 interrupt ? dma channel 1 interrupt ? dma channel 2 interrupt ? dma channel 3 interrupt ? dma channel 4 interrupt ? dma channel 5 interrupt ? host command interrupt ? host transmit data empty ? host receive data full ? essi0 rx data with exception interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-14 dsp56309um/d motorola programming reference ? essi0 rx data interrupt ? essi0 receive last slot interrupt ? essi0 tx data with exception interrupt ? essi0 transmit last slot interrupt ? essi0 tx data interrupt ? essi1 rx data with exception interrupt ? essi1 rx data interrupt ? essi1 receive last slot interrupt ? essi1 tx data with exception interrupt ? essi1 transmit last slot interrupt ? essi1 tx data interrupt ? sci receive data with exception interrupt ? sci receive data ? sci transmit data ? sci idle line ? sci timer ? timer0 overflow interrupt ? timer0 compare interrupt ? timer1 overflow interrupt ? timer1 compare interrupt ? timer2 overflow interrupt lowest timer2 compare interrupt table d-3 interrupt source priorities within an ipl (continued) priority interrupt source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-15 figure d-1 status register (sr) application: date: programmer: sheet 1 of 5 central processor 1514131211109876543210 uzvc 19 18 17 16 23 22 21 20 l lf s1 sm i1 i0 ce sa fv s0 n scaling mode s(1:0) scaling mode 00 01 10 11 no scaling scale down scale up reserved * 0 * 0 interrupt mask i(1:0) exceptions masked 00 01 10 11 none ipl 0 ipl 0, 1 ipl 0, 1, 2 carry over?ow zero negative unnormalized ( u = acc(47) xnor acc(46) ) extension limit fft scaling ( s = acc(46) xor acc(45) ) reserved sixteen-bit compatibilitity double precision multiply mode loop flag do-forever flag sixteenth-bit arithmetic reserved instruction cache enable arithmetic saturation rounding mode core priority cp(1:0) core priority 00 01 10 11 0 (lowest) 1 2 3 (highest) * = reserved, program as 0 mode register (mr) condition code register (ccr) extended mode register (mr) status register (sr) read/write reset = $c00300 cp1 cp0 rm dm sc s e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-16 dsp56309um/d motorola programming reference figure d-2 operating mode register (omr) chip operating modes mod(d:a) reset vector description 0000 x001 x010 x011 x100 x101 x110 x111 1000 $c00000 $ff0000 $ff0000 ? $ff0000 $ff0000 $ff0000 $ff0000 $008000 expanded mode bootstrap from byte wide memory bootstrap through sci reserved host bootstrap pci mode (32-bit wide) host bootstrap 16-bit wide ub mode (isa) host bootstrap 8-bit wide ub mode (dbl strb) host bootstrap 8-bit wide ub mode (sgl strb) expanded mode application: date: programmer: sheet 2 of 5 1514131211109876543210 ebd mc mb ma 19 18 17 16 23 22 21 20 sd brt tas sen cdp1 cdp0 wrp eov eun xys be md core-dma priority cdp(1:0) core-dma priority 00 01 10 11 core vs dma priority dma accesses > core dma accesses = core dma accesses < core * 0 * 0 * 0 * 0 * 0 * 0 * 0 chip operating mode register (com) system stack control status register (scs) extended chip operating mode register (com) x = latched from levels on mode pins operating mode register (omr) read/write reset = $00030x central processor * = reserved, program as 0 burst mode enable ta synchronize select bus release timing stack extension space select extended stack underflow flag extended stack overflow flag extended stack wrap flag stack extension enable memory switch mode ms external bus disable stop delay f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-17 figure d-3 interrupt priority registerecore (iprec) application: date: programmer: sheet 3 of 5 central processor 1514131211109876543210 d1l0 idl2 idl1 ibl2 ibl1 ibl0 ial2 ial1 ial0 interrupt priority x:$ffff read/write d0l1 d0l0 reset = $000000 register (iprec) 23 22 21 20 19 18 16 17 d1l1 ial2 trigger 0 level 1 neg. edge irqa mode ial1 ial0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 ibl2 trigger 0 level 1 neg. edge irqb mode ibl1 ibl0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 icl0 icl1 icl2 idl0 d2l0 d2l1 d3l0 d3l1 d4l0 d4l1 d5l0 d5l1 icl2 trigger 0 level 1 neg. edge irqc mode icl1 icl0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 idl2 trigger 0 level 1 neg. edge irqd mode idl1 idl0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-18 dsp56309um/d motorola programming reference figure d-4 interrupt priority register e peripherals (iprep) application: date: programmer: sheet 4 of 5 central processor * = reserved, program as 0 interrupt priority x:$ffff read/write reset = $000000 register (iprep) hpl1 hpl0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 host ipl s0l1 s0l0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 essi0 ipl 1514131211109876543210 s1l1 s1l0 sol1 s0l0 hpl1 hpl0 23 22 21 20 19 18 16 17 scl0 scl1 t0l0 t0l1 * 0 * 0 * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 * 0 * 0 * 0 * 0 $0 s1l1 s1l0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 essi1 ipl scl1 scl0 enabled ipl 0 0 no ? 0 1 yes 0 1 0 yes 1 1 1 yes 2 sci ipl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-19 figure d-5 phase-locked loop control register (pctl) application: date: programmer: sheet 5 of 5 pll 1514131211109876543210 mf7 mf5 mf4 mf3 mf2 mf1 mf0 19 18 17 16 23 22 21 20 pen cod pd1 pd3 mf6 pd2 xtld xtlr df2 df1 df0 mf11 pd0 pstp mf10 mf9 mf8 pll control register (pctl) x:$fffffd read/write reset = $000000 xtal disable bit (xtld) 0 = enable xtal oscillator 1 = extal driven from an external source clock output disable (cod) 0 = 50% duty cycle clock 1 = pin held in high state crystal range bit (xtlr) 0 = external xtal freq > 200khz 1 = external xtal freq < 200khz predivision factor bits (pd0 e pd3) pd3 e pd0 predivision factor pdf $0 $1 $2 $f 1 2 3 16 multiplication factor bits mf0 e mf11 mf11 e mf0 multiplication factor mf $000 $001 $002 $fff $fff 1 2 3 4095 4096 pstp and pen relationship pstp pen operation during stop pll oscillator 0 1 disabled disabled 1 0 disabled enabled 1 1 enabled enabled division factor bits (df0 e df2) df2 e df0 division factor df $0 $1 $2 $7 2 0 2 1 2 2 2 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-20 dsp56309um/d motorola programming reference figure d-6 host receive and host transmit data registers application: date: programmer: sheet 1 of 6 host 1514131211109876543210 19 18 17 16 23 22 21 20 receive high byte receive middle byte receive low byte host receive data register (hrx) x:$ffec6 read only reset = empty host receive data (usually read by program) 1514131211109876543210 19 18 17 16 23 22 21 20 transmit high byte transmit middle byte transmit low byte host transmit data (usually loaded by program) host transmit data register (htx) x:$ffec7 write only reset = empty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-21 figure d-7 host control and host status registers application: date: programmer: sheet 2 of 6 host 76 5 4 321 0 15 * = reserved, program as 0 * 0 * 0 * 0 dsp side host receive data full 1 = ? read 0 = ? wait hcp hrdf hf1 htde hf0 host flags read only host command pending 1 = ? ready 0 = ? wait host transmit data empty 1 = ? write 0 = ? wait * 0 host staus register (hsr) x:$ffffc3 read only reset = $2 76 5 4 321 0 15 * 0 * 0 * 0 host receive interrupt enable 1 = enable 0 = disable hcie hrie hf3 htie hf2 host flag 2 host command interrupt enable host transmit interrupt enable 1 = enable 0 = disable * 0 host control register (hcr) x:$ffffc2 read /write reset = $0 if hrdf = 1 if htde = 1 1 = enable 0 = disable if hcp = 1 host flag 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-22 dsp56309um/d motorola programming reference figure d-8 host base address and host port control registers application: date: programmer: sheet 3 of 6 host 76 5 4 3 21 0 15 ba5 ba3 ba7 ba4 ba6 * 0 host base address register (hbar) x:$ffffc5 reset = $80 8 ba8 ba9 ba10 * 0 1514131211109876543210 haen hren hcsen ha9en ha8en hgen * = reserved, program as 0 hen * 0 hap hrp hcsp hdds hrod hmux hdsp hasp host port control x:$ffffc4 reset = $0 host acknowledge enable 0 ? hack = gpio host request enable 0 ? hreq/hack = gpio, 1 ? hreq = hreq, if hdrq = 0 host chip select enable 0 ? hcs/hai0 = gpio, 1 ? hcs/ha10 = hc8, if hmux = 0 1 ? hcs/ha10 = hc10, if hmux = 1 host address line 9 enable 0 ? ha9 = gpio, 1 ? ha9 = ha9 host address line 8 enable 0 ? ha8 = gpio, 1 ? ha8 = ha8 host gpio port enable 0 = gpio pins disable, 1 = gpio pin enable host acknowledge priority 0 = hack active low, 1 = hack active high host chip select polarity 0 = hcs active low host dual data strobe 0 = singles stroke, 1 = dual stoke host multiplexed bus 0 = nonmultiplexed, 1 = multiplexed host address strobe polarity 0 = strobe active low, 1 = strobe active high host data strobe polarity 0 = strobe active low, 1 = strobe active high host enable 0 ? hi08 disable 1 ? hi08 enable pins = gpio register (hpcr) read/write if hdrq & hren = 1, hack = hack host request open drain hdrq hrod hren/hew 0 0 1 1 0 1 0 1 1 1 1 1 htrq & hrrq enable 1 = hcs active high host request priority hdrq hrp 0 0 1 1 0 1 0 1 hreq active low hreq active high htrq,hrrq active low htrq,hrrq active high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-23 figure d-9 interrupt control and interrupt status registers application: date: programmer: sheet 4 of 6 host 76 5 4 3 21 0 processor side rreq hf1 treq hf0 init hlend interrupt control register (icr) x:$ read/write transmit request enable dma off 0 = ? interrupts disabled 1 = interrupts enabled dma on 0 = dsp ? host 1 = host ? dsp host flags write only initialize (write only) host little endian receive request enable dma off 0 = ? interrupts disabled 1 = interrupts enabled dma on 0 = host ? dsp 1 = dsp ? host 0 = ? no action 1 = ? initialize dma hdrq * 0 hdrq hreq/htrq hack/hrrq 0 hreq hack 1 htrq hrrq reset = $0 76 5 4 3 21 0 * * = reserved, program as 0 * 0 rxdf hf3 txde hf2 hreq dma trdy interrupt status register (isr) $2 read/write reset = $06 transmit data register empty 0 = wait 1 = write transmitter ready 0 = data in hi 1 = data not in hi dma status 0 = ? dma disabled 1 = ? dma enabled host flags read only receive data register full 0 = wait 1 = read host request 0 = ? hreq deasserted 1 = ? hreq asserted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-24 dsp56309um/d motorola programming reference figure d-10 interrupt vector and command vector registers application: date: programmer: sheet 5 of 6 host 76 5 4 3 21 0 iv0 iv4 iv1 iv3 iv7 iv5 interrupt vector register (ivr) iv2 reset = $0f contains the interrupt vector or number iv6 76 5 4 3 21 0 hc0 hc4 hc1 hc3 hc7 hc5 command vector register (cvr) hc2 reset = $2a contains the host command interrupt address hc6 host vector contains host command interrupt address ? 2 host command handshakes executing host command interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-25 figure d-11 host receive and host transmit data registers application: date: programmer: sheet 6 of 6 host processor side 7070 0 7 host receive data (usually read by program) receive byte registers $7, $6, $5, $4 read only reset = $00 transmit byte registers $7, $6, $5, $4 write only reset = $00 receive byte registers $6 $5 $4 0 0000000 0 7 $7 receive middle byte receive high byte not used receive low byte 7070 0 7 host transmit data (usually loaded by program) $6 $5 $4 0 0000000 0 7 $7 transmit middle byte transmit high byte not used transmit low byte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-26 dsp56309um/d motorola programming reference figure d-12 essi control register a (cra) application: date: programmer: sheet 1 of 4 essi 1514131211109876543210 pm7 pm5 pm4 pm3 pm2 pm1 pm0 19 18 17 16 23 22 21 20 alc wl0 wl1 ssc1 * = reserved, program as 0 pm6 * 0 * 0 * 0 * 0 word length control wl2 wl1 wl0 number of bits/word 0008 00112 01016 01124 1 0 0 32 (data in first 24 bits) 1 0 1 32 (data in last 24 bits) 1 1 0 reserved 1 1 1 reserved essi control register a (crax) essi0 :$ffffb5 read/write essi1 :$ffffa5 read/write reset = $000000 select sc1 as tx#0 drive enable 0 = sc1 functions as serial i/o flag 1 = functions as driver enable of tx#0 external buffer frame rate divider control dc4:0 = $00-$1f (1 to 32) divide ratio for normal mode # of time slots for network prescaler range 0 = ?8 1 = ?1 prescale modulus select pm7:0 = $00-$ff (?1 to ?256) psr = 1 & pm[7:0] = $00 is * 0 wl2 dc4 dc3 dc2 dc1 dc0 psr alignment control 0 = 16-bit data left aligned to bit 23 1 = 16-bit data left aligned to bit 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-27 figure d-13 essi control register b (crb) application: date: programmer: sheet 2 of 4 essi 1514131211109876543210 fsl0 sckd scd2 scd1 scd0 of1 of0 19 18 17 16 23 22 21 20 tie rie rlie reie shfd serial control direction bits scdx = 0 (output) scdx = 1(output) sc0 pin rx clk flag 0 sc1 pin rx frame sync flag 1 sc2 pin tx frame sync tx, rx frame sync teie te0 te1 te2 mod syn ckp transmit 2 enable (syn=1 only) 0 = disable 1 = enable shift direction 0 = msb first 1 = lsb first frame sync relative timing (wl frame sync only) 0 = with 1st data bit 1 = 1 clock cycle earlier than 1st data bit mode select 0 = normal 1 = network clock polarity (clk edge data & frame sync clocked out/in) 0 = out on rising / in on falling 1 = in on rising / out on falling sync/async control (tx & rx transfer together or not) 0 = asynchronous 1 = synchronous essi control register b (crbx) essi0 :$ffffb6 read/write essi1 :$ffffa6 read/write reset = $000000 transmit 1 enable (syn=1 only) 0 = disable 1 = enable transmit interrupt enable 0 = disable 1 = enable receive interrupt enable 0 = disable 1 = enable transmit last slot interrupt enable 0 = disable 1 = enable receive last slot interrupt enable 0 = disable 1 = enable transmit exception interrupt enable 0 = disable 1 = enable receive exception interrupt enable 0 = disable 1 = enable frame sync polarity 0 = high level (positive) 1 = low level (negative) tlie re fsp fsr fsl1 output flag x if syn = 1 and scd1 = 1 ofx ? scx pin clock source direction 0 = external clock 1 = internal clock transmit 0 enable 0 = disable 1 = enable receiver enable 0 = disable 1 = enable fsl1 fsl0 frame sync length tx rx 0 0 word word 0 1 bit word 1 0 bit bit 1 1 word bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-28 dsp56309um/d motorola programming reference figure d-14 essi status register (ssisr) application: date: programmer: sheet 3 of 4 essi 76543210 if0 if1 rfs tue roe rdf tde * = reserved, program as 0 23 * 0 tfs receive frame sync 0 = ? wait 1 = ? frame sync occurred transmitter underrun error flag 0 = ? ok 1 = ? error receiver overrun error flag 0 = ? ok 1 = ? error transmit data register empty 0 = ? wait 1 = ? write transmit frame sync 0 = ? sync inactive 1 = ? sync active receive data register full 1 = ? read serial input flag 0 if scd0 = 0, syn = 1, & te1 = 0 latch sc0 on fs serial input flag 1 if scd1 = 0, syn = 1, & te2 = 0 latch sc0 on fs 0 = ? wait ssi status bits ssi status register (ssisrx) essi0: $ffffb7 (read) essi1: $ffffa7 (read) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-29 figure d-15 essr transmit and receive slot mask registers (tsm, rsm) application: date: programmer: sheet 4 of 4 essi 1514131211109876543210 rs23 rs21 rs20 rs19 rs18 rs17 rs16 16 23 * = reserved, program as 0 rs22 * 0 rs31 rs30 rs29 rs28 rs27 ssi receive slot mask a rsmax essi0: $ffffb2 read/write essi1: $ffffa2 read/write reset = $ffff ssi receive slot mask b rsmbx essi0: $ffffb1 read/write essi1: $ffffa1 read/write reset = $ffff essi transmit slot mask a tsmax essi0: $ffffb4 read/write essi1: $ffffa4 read/write reset = $ffff essi transmit slot mask b tsmbx essi0: $ffffb3 read/write essi1: $ffffa3 read/write reset = $ffff essi receive slot mask a essi receive slot mask b essi transmit slot mask a essi transmit slot mask b 1514131211109876543210 rs7 rs5 rs4 rs3 rs2 rs1 rs0 16 23 * = reserved, program as 0 rs6 * 0 rs15 rs14 rs13 rs12 rs11 1514131211109876543210 ts23 ts21 ts20 ts19 ts18 ts17 ts16 16 23 * = reserved, program as 0 ts22 * 0 ts31 ts30 ts29 ts28 ts27 1514131211109876543210 ts7 ts5 ts4 ts3 ts2 ts1 ts0 16 23 * = reserved, program as 0 ts6 * 0 ts15 ts14 ts13 ts12 ts11 ssi receive slot mask 0 = ignore time slot 1 = active time slot ssi receive slot mask 0 = ignore time slot 1 = active time slot ssi transmit slot mask 0 = ignore time slot 1 = active time slot * 0 ts10 ts9 ts8 ssi transmit slot mask 0 = ignore time slot 1 = active time slot ts26 ts25 ts24 * 0 rs10 rs9 rs8 rs26 rs25 rs24 * 0 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-30 dsp56309um/d motorola programming reference figure d-16 sci control register (scr) application: date: programmer: sheet 1 of 3 sci sci control register (scr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 woms wake sbk ssftd wds2 wds1 wds0 23 * rwu * 0 sckp stir tmie tie rie ilie te re sci shift direction 0 = lsb first 1 = msb first send break 0 = send break, then revert 1 = continually send breaks receiver wakeup enable 0 = receiver has awakened 1 = wakeup function enabled receiver enable 0 = receiver disabled 1 = receiver enabled wired-or mode select 1 = multidrop 0 = point to point wakeup mode select 0 = idle line wakeup 1 = address bit wakeup word select bits 0 0 0 = 8-bit synchronous data (shift register mode) 0 0 1 = reserved 0 1 0 = 10-bit asynchronous (1 start, 8 data, 1 stop) 0 1 1 = reserved 1 0 0 = 11-bit asynchronous (1 start, 8 data, even parity, 1 stop) 1 0 1 = 11-bit asynchronous (1 start, 8 data, odd parity, 1 stop) 1 1 0 = 11-bit multidrop (1 start, 8 data, data type, 1 stop) 1 1 1 = reserved transmitter enable 0 = transmitter disable 1 = transmitter enable transmit interrupt enable 0 = transmit interrupts disabled 1 = transmit interrupts enabled idle line interrupt enable 0 = idle line interrupt disabled 1 = idle line interrupt enabled receive interrupt enable sci clock polarity 0 = clock polarity is positive 1 = clock polarity is negative sci timer interrupt rate 0 = ? 32, 1 = ? 1 timer interrupt enable 0 = timer interrupts disabled 1 = timer interrupts enabled 0 = receive interrupt disabled 1 = idle line interrupt enabled register (scr) address x:$ffff9c read/write sci control reie 16 sci receive exception inerrupt 0 = receive interrupt disable 1 = receive interrupt enable = reserved, program as 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-31 figure d-17 sci status and clock control registers (ssr, sccr) application: date: programmer: sheet 2 of 3 sci sci clock control register (sccr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cd7 cd5 cd4 cd3 cd2 cd1 cd0 23 * = reserved, program as 0 cd6 * 0 tcm rcm scp cod cd11 23 76543210 tdre trne * = reserved, program as 0 cd10 cd9 cd8 * 0 rdrf $0 idle or pe fe r8 sci status register (ssr) address x:$ffff93 read only reset = $000003 received bit 8 0 = data 1 = address framing error flag 0 = no error 1 = no stop bit detected parity error flag 0 = no error 1 = incorrect parity detected overrun error flag 0 = no error 1 = overrun detected idle line flag 0 = idle not detected 1 = idle state receive data register full 0 = receive data register empty 1 = receive data register full transmitter data register empty 0 = transmitter data register full 1 = transmitter data register empty transmitter empty 0 = transmitter full 1 = transmitter empty clock divider bits cd11 e cd0) cd11 e cd0 i cyc rate $000 i cyc /1 $001 i cyc /2 $002 i cyc /3 $ffe i cyc /4095 $fff i cyc /4096 sci clock prescaler 0 = ?1 1 = ? 8 sci status register (ssr) clock out divider 0 = divide clock by 16 before feed to sclk 1 = feed clock to directly to sclk clock divider bits cd11 e cd0) tcm rcm tx clock rx clock sclk pin mode 0 0 internal internal output synchronous/asynchronous 0 1 internal external input asynchronous only 1 0 external internal input asynchronous only 1 1 external external input synchronous/asynchronous receiver clock mode/source 0 = internal clock for receiver 1 = external clock from sclk transmitter clock mode/source 0 = internal clock for transmitter 1 = external clock from sclk $3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-32 dsp56309um/d motorola programming reference figure d-18 sci receive and transmit data registers (srx, trx) application: date: programmer: sheet 3 of 3 sci 23 16 15 8 7 0 x:$ffff97 x:$ffff96 x:$ffff95 stx stx stx x0 a b c sci transmit data registers address x:$ffff95 e x:$ffff97 write reset = xxxxxx unpacking txd sci transmit sr sci transmit data registers sci receive data registers x:$ffff94 stxa 23 16 15 8 7 0 srx srx srx a b c packing rxd sci receive sr sci receive data registers address x:$ffff98 e x:$ffff9a read reset = xxxxxx x:$ffff9a x:$ffff99 x:$ffff98 note: stx is the same register decoded at four different addresses note: stx is the same register decoded at three different addresses f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-33 figure d-19 timer prescaler load/count register (tplr, tpcr) application: date: programmer: sheet 1 of 3 timers 1514131211109876543210 19 18 17 16 23 22 21 20 ps0 ps1 * 0 prescaler preload value (pl [0:20]) * = reserved, program as 0 1514131211109876543210 19 18 17 16 23 22 21 20 * 0 current value of prescaler counter (pc [0:20]) timer prescaler load register tplr:$ffff83 read/write reset = $000000 timer prescaler count register tpcr:$ffff82 read only reset = $000000 * = reserved, program as 0 ps (1:0) prescaler clock source 00 internal clk/2 01 tio0 10 tio1 11 tio2 * 0 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-34 dsp56309um/d motorola programming reference figure d-20 timer control/status register (tcsr) application: date: programmer: sheet 2 of 3 1514131211109876543210 tc3 tc1 tc0 tcie tqie te 19 18 17 16 23 22 21 20 tcf tc2 pce do di dir tof trm inv timers * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 timer enable bit 0 0 = timer disabled 1 = timer enabled timer overflow interrupt enable bit 1 0 = overflow interrupts disabled 1 = overflow interrupts enabled inverter bit 8 0 = 0- to-1 transitions on tio input increment the counter, or high pulse width measured, or high pulse output on tio 1 = 1-to-0 transitions on tio input increment the counter, or low pulse width measured, or low pulse output on tio timer compare interrupt enable bit 2 0 = compare interrupts disabled 1 = compare interrupts enabled timer control/status register tcsr0:$ffff8f read/write tcsr1:$ffff8b read/write tcsr2:$ffff87 read/write reset = $000000 * = reserved, program as 0 timer control bits 4 e 7 (tc0 e tc3) tc (3:0) tio clock mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 gpio output output input input input input output e output output e e e e e internal internal internal external internal internal internal internal e internal internal e e e e e timer timer pulse timer toggle event counter input width input period capture pulse width modulation reserved watchdog pulse watchdog toggle reserved reserved reserved reserved reserved timer reload mode bit 9 1 = timer is reloaded when selected condition occurs 0 = timer operates as a free running counter timer overflow flag bit 20 0 = 1 has been written to tcsr(tof), or timer overflow interrupt serviced 1 = counter wraparound has occurred direction bit 11 0 = tio pin is input 1 = tio pin is output data output bit 13 0 = zero written to tio pin 1 = one written to tio pin data input bit 12 0 = zero read on tio pin 1 = one read on tio pin timer compare flag bit 21 0 = 1 has been written to tcsr(tcf), or timer compare interrupt serviced 1 = timer compare has occurred prescaled clock enable bit 15 0 = clock source is clk/2 or tio 1 = clock source is prescaler output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-35 figure d-21 timer load, compare, count registers (tlr, tcpr, tcr) application: date: programmer: sheet 3 of 3 timers 1514131211109876543210 19 18 17 16 23 22 21 20 timer reload value timer load register tlr0:$ffff8e write only reset = $000000 tlr1:$ffff8a write only tlr2:$ffff86 write only timer compare register tcpr0:$ffff8d read/write reset = $000000 tcpr1:$ffff89 read/write tcpr2:$ffff85 read/write timer count register tcr0:$ffff8c read only tcr1:$ffff88 read only tcr2:$ffff84 read only reset = $000000 1514131211109876543210 19 18 17 16 23 22 21 20 value compared to counter value 1514131211109876543210 19 18 17 16 23 22 21 20 timer count value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-36 dsp56309um/d motorola programming reference figure d-22 host data direction and host data registers (hddr, hdr) application: date: programmer: sheet 1 of 4 gpio 1514131211109876543210 dr5 dr4 dr3 dr2 dr1 dr0 dr6 dr15 dr14 dr13 dr12 dr8 dr11 dr9 dr10 direction register x:$ffffc8 reset = $0 (hddr) write host data drx = 0 ? hix is input drx = 1 ? hix is output 1514131211109876543210 d5 d4 d3 d2 d1 d0 d6 d15 d14 d13 d12 d8 d11 d9 d10 register x:$ffffc9 reset = undefined (hdr) write host data drx holds value of corresponding hi08 gpio pin. dr7 d7 function depends on hddr. port b (hi08) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-37 figure d-23 port c registers (pcrc, prrc, pdrc) application: date: programmer: sheet 2 of 4 gpio 236543210 pc5 pc4 pc3 pc2 pc1 pc0 port c control register x:$ffffbf reset = $0 (pcrc) readwrite * 0 * = reserved, program as 0 * 0 pcn = 1 ? port pin configured as essi pcn = 0 ? port pin configured as gpio port c (essi0) 236543210 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 port c direction register x:$ffffbe reset = $0 (prrc) readwrite * 0 * 0 pdcn = 1 ? port pin is output pdcn = 0 ? port pin is input 236543210 pd5 pd4 pd3 pd2 pd1 pd0 port c gpio data register x:$ffffbd reset = $0 (pdrc) readwrite * 0 * 0 port pin n is gpio input, then pdn reflects the value on port pin n if port pin n is gpio output, then value written to pdn is reflected on port pin n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-38 dsp56309um/d motorola programming reference figure d-24 port d registers (pcrd, prrd, pdrd) application: date: programmer: sheet 3 of 4 gpio 236543210 pc5 pc4 pc3 pc2 pc1 pc0 port d control register x:$ffffaf reset = $0 (pcrd) readwrite * 0 * = reserved, program as 0 * 0 pcn = 1 ? port pin configured as essi pcn = 0 ? port pin configured as gpio port d (essi1) 236543210 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 port d direction register x:$ffffae reset = $0 (prrd) readwrite * 0 * 0 pdcn = 1 ? port pin is output pdcn = 0 ? port pin is input 236543210 pd5 pd4 pd3 pd2 pd1 pd0 port d gpio data register x:$ffffad reset = $0 (pdrd) readwrite * 0 * 0 port pin n is gpio input, then pdn reflects the value on port pin n if port pin n is gpio output, then value written to pdn is reflected on port pin n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming reference motorola dsp56309um/d d-39 figure d-25 port e registers (pcre, prre, pdre) application: date: programmer: sheet 4 of 4 gpio 236543210 pc2 pc1 pc0 port e control register x:$ffff9f reset = $0 (pcre) readwrite * 0 * = reserved, program as 0 * 0 pcn = 1 ? port pin configured as sci pcn = 0 ? port pin configured as gpio port e (sci) 236543210 pdc2 pdc1 pdc0 port e direction register x:$ffff9e reset = $0 (prre) readwrite * 0 * 0 pdcn = 1 ? port pin is output pdcn = 0 ? port pin is input 236543210 pd2 pd1 pd0 port e gpio data register x:$ffff9d reset = $0 (pdre) readwrite * 0 * 0 port pin n is gpio input, then pdn reflects the value on port pin n if port pin n is gpio output, then value written to pdn is reflected on port pin n * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d-40 dsp56309um/d motorola programming reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56309um/d i-1 index a a0ea17 signals 2-9 aa0eaa3 signals 2-10 adder modulo 1-9 offset 1-9 reverse-carry 1-9 address attribute signals 2-10 address bus 2-3 signals 2-9 address generation unit 1-9 addressing modes 1-10 agu 1-9 alc bit 7-13 alignment control bit (alc) 7-13 applications 1-7 asynchronous/synchronous bit (syn) 7-18 b ba3eba10 bits 6-12 barrel shifter 1-8 base address bits (ba3eba10) 6-12 bb signal 2-13 bclk signal 2-13 bclk signal 2-13 bg signal 2-12 bootstrap 4-4 bootstrap from byte-wide external memory 4-7 bootstrap program options invoking 4-5 bootstrap rom 3-7 bootstrap through hi08 (68302/68360) 4-9 bootstrap through hi08 (isa) 4-8 bootstrap through hi08 (multiplexed) 4-9 bootstrap through hi08 (non-multiplexed) 4-8 bootstrap through sci 4-7 boundary scan description language pbga c-8 tqfp c-2 boundary scan register (bsr) 11-7 br signal 2-12 break 8-9 breakpoint 0 and 1 event bits (bt0ebt1) 10-14 breakpoint 0 condition code select bits (cc00ecc01) 10-13 breakpoint 0 read/write select bits (rw00erw01) 10-12 breakpoint 1 condition code select bits (cc10ecc11) 10-14 breakpoint 1 read/write select bits (rw10erw11) 10-13 bsdl listing pbga c-8 tqfp c-2 bsr register 11-7 bt0ebt1 bits 10-14 bus address 2-4 data 2-4 external address 2-9 external data 2-9 multiplexed 2-4 non-multiplexed 2-4 bus busy signal (bb ) 2-13 bus clock not signal (bclk ) 2-13 bus clock signal (bclk) 2-13 bus control 2-3 bus grant signal (bg ) 2-12 bus parking 2-13 bus request signal (br ) 2-12 buses internal 1-13 bypass instruction 11-11 c cas signal 2-13 cc00ecc01 bits 10-13 cc10ecc11 bits 10-14 cd0ecd11 bits 8-16 central processing unit (cpu) 1-3 ckp bit 7-18 clamp instruction 11-10 clkgen 1-11 clkout signal 2-8 clock 1-7 , 2-3 clock divider bits (cd0ecd11) 8-16 clock generator (clkgen) 1-11 clock out divider bit (cod) 8-16 clock output signal (clkout) 2-8 clock polarity bit (ckp) 7-18 clock signals 2-7 clock source direction bit (sckd) 7-16 cmos 1-7 cod bit 8-16 code compatible 1-7 column address strobe signal (cas ) 2-13 cra register 7-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d i-2 dsp56309um/d motorola bits 0e7?prescale modulus select bits (pm0epm7) 7-11 bits 8e10?reserved bits 7-11 bit 11?prescaler range bit (psr) 7-11 bits 12e16?frame rate divider control bits (dc4edc0) 7-12 bit 17?reserved bit 7-13 bit 18?alignment control bit (alc) 7-13 bits 19e21?word length control bits (wl0ewl1) 7-14 bit 22?select sc1 as transmitter 0 drive enable bit (ssc1) 7-14 bit 23?reserved bit 7-14 reserved bits?bit 17 7-13 reserved bits?bit 23 7-14 reserved bits?bits 8e10 7-11 crb register bits 0e1?serial output flag bits (of0eof1) 7-15 bit 2?serial control 0 direction bit (scd0) 7-16 bit 3?serial control 1 direction bit (scd1) 7-16 bit 4?serial control 2 direction bit (scd2) 7-16 bit 5?clock source direction bit (sckd) 7-16 bit 6?shift direction bit (shfd) 7-17 bits 7e8?frame sync length bits (fsl1efsl0) 7-17 bit 9?frame sync relative timing bit (fsr) 7-17 bit 10?frame sync polarity bit (fsp) 7-17 bit 11?clock polarity bit (ckp) 7-18 bit 12?asynchronous/synchronous bit (syn) 7-18 bit 13?essi mode select bit (mod) 7-20 bit 14?essi transmit 2 enable bit (te2) 7-22 bit 15?essi transmit 1 enable bit (te1) 7-23 bit 16?essi transmit 0 enable bit (te0) 7-24 bit 17?essi receive enable bit (re) 7-26 bit 18?essi transmit interrupt enable bit (tie) 7-26 bit 19?essi receive interrupt enable bit (rie) 7-26 bit 20?essi transmit last slot interrupt enable bit (tlie) 7-26 bit 21?essi receive last slot interrupt enable bit (rlie) 7-27 bit 22?essi transmit exception interrupt enable bit (teie) 7-27 bit 23?essi receive exception interrupt enable bit (reie) 7-27 crystal input 2-8 cvr register bits 0e6?host vector bits (hv0ehv6) 6-25 d d0ed23 2-10 data alu 1-8 registers 1-8 data bus 2-3 signals 2-10 data output bit (do) 9-14 dc4edc0 bits 7-12 de signal 2-37 , 10-4 debug event signal (de signal) 10-4 debug mode in once module 10-16 debug_request instruction 11-11 executing during stop state 10-17 executing during wait state 10-17 executing in once module 10-17 direct memory access (dma) 1-15 divide factor (df) 1-11 dma 1-15 triggered by timer 9-27 do bit 9-14 do loop 1-10 double data strobe 2-4 double host request bit (hdrq) 6-23 dram 1-13 ds 2-4 dsp56300 core 1-3 , 1-6 dsp56300 family manual 1-3 , 1-7 dsp56303 functional signal groupings 2-3 signal groupings 2-3 dsp56303 technical data 1-3 e enable_once instruction 11-11 enhanced synchronous serial interface (essi) 1-16 , 2-3 , 2-25 , 2-28 enhanced synchronous serial interface 0 2-24 enhanced synchronous serial interface 1 2-28 equates biu b-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f motorola dsp56309um/d i-3 bus interface unit b-13 direct memory access b-10 dma b-10 enhanced serial communication interface b-5 essi b-5 exception processing b-7 hi08 b-3 host interface b-3 i/o port programming b-3 interrupt b-15 phase locked loop b-12 pll b-12 sci b-4 serial communication interface b-4 timer module b-9 essi 2-4 after reset 7-36 asynchronous operating mode 7-40 frame sync length 7-41 frame sync polarity 7-42 frame sync selection 7-41 frame sync word length 7-41 gpio functionality 7-43 initialization 7-36 interrupts 7-37 network mode 7-40 normal mode 7-40 operating mode 7-36 operating modes 7-40 port control register (pcr) 7-43 port data register (pdr) 7-45 port direction register (prr) 7-44 programming model 7-8 synchronous operating mode 7-40 essi control register a (cra) 7-11 essi mode select bit (mod) 7-20 essi receive data register (rx) 7-33 essi receive enable bit (re) 7-26 essi receive exception interrupt enable bit (reie) 7-27 essi receive interrupt enable bit (rie) 7-26 essi receive last slot interrupt enable bit (rlie) 7-27 essi receive shift register 7-33 essi receive slot mask registers (rsma, rsmb) 7-35 essi status register (ssisr) 7-27 essi time slot register (tsr) 7-34 essi transmit 0 enable bit (te0) 7-24 essi transmit 1 enable bit (te1) 7-23 essi transmit 2 enable bit (te2) 7-22 essi transmit data registers (tx2, tx1, tx0) 7-34 essi transmit exception interrupt enable bit (teie) 7-27 essi transmit interrupt enable bit (tie) 7-26 essi transmit last slot interrupt enable bit (tlie) 7-26 essi transmit shift registers 7-33 essi transmit slot mask registers (tsma, tsmb) 7-34 essi0 2-24 essi0 (gpio) 5-3 essi1 2-28 essi1 (gpio) 5-4 ex bit 10-5 exception processing equates b-7 exit command bit (ex) 10-5 expanded mode 4-6 extal 2-7 extal signal 2-7 external address bus 2-9 external bus control 2-9 , 2-11 , 2-12 external clock/crystal input 2-7 external data bus 2-9 external interrupt request a signal 2-14 external interrupt request b signal 2-15 external interrupt request c signal 2-15 external interrupt request d signal 2-16 external memory expansion port 2-9 extest instruction 11-8 f fe bit 8-15 frame rate divider control bits (dc4edc0) 7-12 frame sync length bits (fsl1efsl0) 7-17 frame sync polarity bit (fsp) 7-17 frame sync relative timing bit (fsr) 7-17 frame sync selection essi 7-41 framing error flag bit (fe) 8-15 frequency operation 1-7 fsl1efsl0 bits 7-17 fsp bit 7-17 fsr bit 7-17 functional groups 2-4 g general purpose input/output (gpio) 2-34 global data bus 1-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . h i-4 dsp56309um/d motorola go command bit (go) 10-6 gpio 1-15 , 2-4 , 2-34 on hi08 6-30 timers 2-4 gpio (essi0, port c) 5-3 gpio (essi1, port d) 5-4 gpio (hi08, port b) 5-3 gpio (sci, port e) 5-4 gpio (timer) 5-4 gpio functionality on essi 7-43 ground 2-3 , 2-6 address bus 2-6 bus control 2-7 data bus 2-7 essi 2-7 host interface 2-7 pll 2-6 quiet 2-6 sci 2-7 timer 2-7 h h0eh7 signals 2-18 ha0 signal 2-18 ha1 signal 2-19 ha2 signal 2-19 ha8 signal 2-19 ha10 signal 2-21 ha9 signal 2-19 ha8en bit 6-13 ha9en bit 6-13 had0ehad7 signals 2-18 haen bit 6-14 hap bit 6-16 hardware stack 1-10 has /has 2-18 hasp bit 6-15 hbar register 6-12 bits 0e7?base address bits (ba3eba10) 6-12 reserved bits?bits 5e15 6-12 hcie bit 6-10 hcp bit 6-11 hcr register 6-9 , 6-10 bit 0?host receive interrupt enable bit (hrie) 6-10 bit 1?host transmit interrupt enable bit (htie) 6-10 bit 2?host command interrupt enable bit (hcie) 6-10 bits 3, 4?host flag 2 and 3 bits (hf2, hf3) 6-10 reserved bits?bits 5e15 6-10 hcs signal 2-21 hcsen bit 6-13 hcsp bit 6-16 hddr register 6-17 hdds bit 6-15 hdr register 6-17 hdrq bit 6-23 hds signal 2-20 hdsp bit 6-14 hen bit 6-14 hf0 bit 6-24 hf0, hf1 bits 6-11 hf1 bit 6-24 hf2 bit 6-27 hf2, hf3 bits 6-10 hf3 bit 6-27 hgen bit 6-13 hi08 1-16 , 2-3 , 2-4 , 2-16 , 2-18 , 2-19 , 2-21 , 6-3 (gpio) 5-3 data transfer 6-31 dsp side control registers 6-8 dsp side data registers 6-8 dsp side registers after reset 6-18 dsp to host data word 6-5 handshaking protocols 6-5 interrupts 6-5 mapping 6-4 transfer modes 6-5 external host programmer?s model 6-20 gpio 6-30 hi08 to dsp core interface 6-3 hi08 to host processor interface 6-4 host base address register (hbar) 6-12 host control register (hcr) 6-9 , 6-10 host data direction register (hddr) 6-17 host data register (hdr) 6-17 host port control register (hpcr) 6-12 host receive data register (hrx) 6-8 host side interface control register (icr) 6-22 interface status register (isr) 6-26 interface vector register (ivr) 6-28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . h motorola dsp56309um/d i-5 receive byte registers (rxh, rxm, rxl) 6-28 transmit byte registers (txh, txm, txl) 6-29 host side registers after reset 6-30 host status register (hsr) 6-11 host to dsp data word 6-3 handshaking protocols 6-4 instructions 6-4 mapping 6-3 transfer modes 6-3 host transmit data register (htx) 6-9 polling 6-31 registers 6-7 servicing interrupts 6-32 hi-z instruction 11-10 hlend bit 6-24 hmux bit 6-15 host acknowledge enable bit (haen) 6-14 host acknowledge polarity bit (hap) 6-16 host acknowledge signal (hack /hack 2-23 host address 10 signal (ha10) 2-21 host address 8 signal (ha8) 2-19 host address 9 signal (ha9) 2-19 host address input 0 signal (ha0) 2-18 host address input 1 signal (ha1) 2-19 host address input 2 signal (ha2) 2-19 host address line 8 enable bit (ha8en) 6-13 host address line 9 enable bit (ha9en) 6-13 host address signal had0ehad7) 2-18 host address strobe polarity bit (hasp) 6-15 host address strobe signal (has /has) signal 2-18 host base address register (hbar) 6-12 host chip select enable bit (hcsen) 6-13 host chip select polarity bit (hcsp) 6-16 host chip select signal (hcs) 2-21 host command interrupt enable bit (hcie) 6-10 host command pending bit (hcp) 6-11 host control register (hcr) 6-9 , 6-10 host data direction register (hddr) 6-17 host data register (hdr) 6-17 host data signal (h0eh7) 2-18 host data strobe polarity bit (hdsp) 6-14 host data strobe signal (hds /hds) 2-20 host dual data strobe bit (hdds) 6-15 host enable bit (hen) 6-14 host flag 0 and 1 bits (hf0, hf1) 6-11 host flag 0 bit (hf0) 6-24 host flag 1 bit (hf1) 6-24 host flag 2 and 3 bits (hf2, hf3) 6-10 host flag 2 bit (hf2) 6-27 host flag 3 bit (hf3) 6-27 host gpio port enable bit (hgen) 6-13 host interface 1-16 , 2-3 , 2-4 , 2-16 , 2-18 , 2-19 , 2-21 , 6-3 host little endian bit (hlend) 6-24 host multiplexed bus bit (hmux) 6-15 host port configuration 2-17 usage considerations 2-16 host port control register (hpcr) 6-12 host read data signal (hrd /hrd) signal 2-20 host read/write signal (hrw) 2-20 host receive data full bit (hrdf) 6-11 host receive data register (hrx) 6-8 host receive interrupt enable bit (hrie) 6-10 host request double 2-4 single 2-4 host request enable bit (hren) 6-14 host request open drain bit (hrod) 6-14 host request polarity bit (hrp) 6-16 host request signal (hreq /hreq 2-22 host status register (hsr) 6-11 host transmit data empty bit (htde) 6-11 host transmit data register (htx) 6-9 host transmit interrupt enable bit (htie) 6-10 host vector bits (hv0ehv6) 6-25 host write data signal (hwr /hwr) 2-20 hpcr register 6-12 bit 0?host gpio port enable bit (hgen) 6-13 bit 1?host address line 8 bit (ha8en) 6-13 bit 2?host address line 9 bit (ha9en) 6-13 bit 3?host chip select enable bit (hcsen) 6-13 bit 4?host request enable bit (hren) 6-14 bit 5?host acknowledge enable bit (haen) 6-14 bit 6?host enable bit (hen) 6-14 bit 7?reserved bit 6-14 bit 8?host request open drain bit (hrod) 6-14 bit 9?host data strobe polarity bit (hdsp) 6-14 bit 10?host address strobe polarity bit (hasp) 6-15 bit 11?host multiplexed bus bit (hmux) 6-15 bit 12?host dual data strobe bit (hdds) 6-15 bit 13?host chip select polarity bit (hcsp) 6-16 bit 14?host request polarity bit (hrp) 6-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i i-6 dsp56309um/d motorola bit 15?host acknowledge polarity bit (hap) 6-16 reserved bit?bit 7 6-14 hr 2-4 hrd /hrd 2-20 hrdf bit 6-11 hren bit 6-14 hrie bit 6-10 hrod bit 6-14 hrp bit 6-16 hrrq /hrrq 2-23 hrw 2-20 hrx register 6-8 hsr register 6-11 bit 0?host receive data full bit (hrdf) 6-11 bit 1?host transmit data empty bit (htde) 6-11 bit 2?host command pending bit (hcp) 6-11 bits 3, 4?host flag 0 and 1 bits (hf0, hf1) 6-11 reserved bits?bits 5e15 6-11 htde bit 6-11 htie bit 6-10 htrq /htrq 2-22 htx register 6-9 hv0ehv6 bits 6-25 hwr /hwr signal 2-20 i icr register 6-22 bit 0?receive request enable bit (rreq) 6-23 bit 1?transmit request enable bit (treq) 6-23 bit 2?double host request bit (hdrq) 6-23 bit 3?host flag 0 bit (hf0) 6-24 bit 4?host flag 1 bit (hf1) 6-24 bit 5?host little endian bit (hlend) 6-24 bit 6?reserved bit 6-24 reserved bit?bit 6 6-24 idcode instruction 11-9 idle bit 8-14 idle line flag bit (idle) 8-14 idle line interrupt enable bit (ilie) 8-11 if0 bit 7-28 if1 bit 7-28 ilie bit 8-11 ime bit 10-8 instruction cache 3-3 location 3-8 instruction set 1-7 interface control register (icr) 6-22 interface status register (isr) 6-26 interface vector register (ivr) 6-28 internal buses 1-13 interrupt 1-10 essi 7-37 priority levels 4-12 servicing on hi08 6-32 sources 4-9 interrupt and mode control 2-3 , 2-14 , 2-15 interrupt control 2-14 , 2-15 interrupt equates b-15 interrupt mode enable bit (ime) 10-8 interrupt priority register p (ipr?p) 4-13 interrupts dma equates b-15 ending address b-16 essi equates b-16 host equates b-16 non-maskable b-15 request pins b-15 sci equates b-16 timer equates b-15 inv bit 9-11 inverter bit (inv) 9-11 ipr?p 4-13 isr register 6-26 bit 0?receive data register full bit (rxdf) 6-26 bit 1?transmit data register empty bit (txde) 6-27 bit 2?transmitter ready bit (trdy) 6-27 bit 3?host flag 2 bit (hf2) 6-27 bit 4?host flag 3 bit (hf3) 6-27 bit 5?reserved bit 6-27 bit 6?reserved bit 6-27 reserved bits?bits 5,6 6-27 ivr register 6-28 j joint test action group (jtag) 11-3 jtag 1-11 , 2-35 jtag instructions bypass instruction 11-11 clamp instruction 11-10 debug_request instruction 11-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . k motorola dsp56309um/d i-7 enable_once instruction 11-11 extest instruction 11-8 hi-z instruction 11-10 idcode instruction 11-9 sample/preload instruction 11-9 jtag/once interface signals debug event signal (de signal) 10-4 k keeper, weak 2-24 , 2-25 , 2-26 , 2-27 , 2-28 , 2-29 , 2-30 , 2-31 , 2-32 , 2-33 , 2-34 , 2-35 l la register 1-10 lc register 1-10 logic 1-7 loop address register (la) 1-10 loop counter register (lc) 1-10 m mac 1-9 manual conventions 1-5 mbo bit 10-8 mbs0embs1 bits 10-12 memory bootstrap rom 3-7 enabling breakpoints 10-18 external expansion port 1-13 maps 3-9 on-chip 1-12 program ram 3-6 x data ram 3-6 y data ram 3-7 memory breakpoint occurrence bit (mbo) 10-8 memory breakpoint select bits (mbs0embs1) 10-12 memory configuration 3-7 memory spaces 3-7 ram 3-8 mf bits 4-18 mips 1-7 mod bit 7-20 moda/irqa 2-14 modb/irqb 2-15 modc/irqc 2-15 modd/irqd 2-16 mode control 2-14 , 2-15 mode select bit (mod) 7-20 mode select a signal 2-14 mode select b signal 2-15 mode select c signal 2-15 mode select d signal 2-16 modulo adder 1-9 multiplexed bus 2-4 multiplication factor bits (mf) 4-18 multiplier-accumulator (mac) 1-8 , 1-9 n non-maskable interrupt 2-8 , 2-9 non-multiplexed bus 2-4 o obcr register 10-12 bits 0e1?memory breakpoint select bits (mbs0embs1) 10-12 bits 2e3?breakpoint 0 read/write select bits (rw00erw01) 10-12 bits 4e5?breakpoint 0 condition code select bits (cc00ecc01) 10-13 bits 6e7?breakpoint 1 read/write select bits (rw10erw11) 10-13 bits 8e9?breakpoint 1 condition code select bits (cc10ecc11) 10-14 bits 10e11?breakpoint 0 and 1 event select bits (bt0ebt1) 10-14 reserved bits?bits 12e15 10-15 ocr register bits 0e4?register select bits (rs0ers4) 10-5 bit 5?exit command bit (ex) 10-5 bit 6?go command bit (go) 10-6 bit 7?read/write command bit (r/w ) 10-6 odec 10-8 of0eof1 bits 7-15 offset adder 1-9 ogdbr register 10-20 omac0 comparator 10-11 omac1 comparator 10-11 omal register 10-11 ombc counter 10-14 omlr0 register 10-11 omlr1 register 10-11 omr register 1-11 once 1-4 commands 10-23 controller 10-4 trace logic 10-15 once breakpoint control register (obcr) 10-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . p i-8 dsp56309um/d motorola once command register (ocr) 10-5 once decoder (odec) 10-8 once gdb register (ogdbr) 10-20 once memory address comparator 0 (omac0) 10-11 once memory address comparator 1 (omac1) 10-11 once memory address latch register (omal) 10-11 once memory breakpoint counter (ombc) 10-14 once memory limit register 0 (omlr0) 10-11 once memory limit register 1 (omlr1) 10-11 once module 1-12 , 10-3 checking for debug mode 10-24 displaying a specified register 10-26 displaying x data memory 10-26 interaction with jtag port 10-29 polling the jtag instruction shift register 10-24 reading the trace buffer 10-25 returning to normal mode 10-28 saving pipeline information 10-25 once pab register for decode register (opabdr) 10-20 once pab register for execute (opabex) 10-20 once pab register for fetch register (opabfr) 10-20 once pil register (opilr) 10-19 once program data bus register (opdbr) 10-19 once status and control register (oscr) 10-8 once trace counter (otc) 10-16 once/jtag 2-4 debug event signal (de ) 2-37 test clock signal (tck) 2-35 test data input signal (tdi) 2-35 test data output signal (tdo) 2-36 test mode select signal (tms) 2-36 once/jtag port 2-3 on-chip emulation (once) module 1-12 on-chip emulation module 10-3 on-chip memory 1-12 program 3-6 x data ram 3-6 y data ram 3-7 opabdr register 10-20 opabex register 10-20 opabfr register 10-20 opdbr register 10-19 operating 4-3 operating mode 4-3 bootstrap from byte-wide external memory 4-7 bootstrap thorugh hi08 (68302/68360) 4-9 bootstrap through hi08 (isa) 4-8 bootstrap through hi08 (multiplexed) 4-9 bootstrap through hi08 (non-multiplexed) 4-8 bootstrap through sci 4-7 essi 7-36 , 7-40 expanded 4-6 expanded mode 4-6 operating mode register (omr) 1-11 operating modes 4-3 opilr register 10-19 or bit 8-14 oscr register 10-8 bit 0?trace mode enable bit (tme) 10-8 bit 1?interrupt mode enable bit (ime) 10-8 bit 2?software debug occurrence bit (swo) 10-8 bit 3?memory breakpoint occurrence bit (mbo) 10-8 bit 4?trace occurrence bit (to) 10-9 bit 5?reserved bit 10-9 reserved bits?bits 8e23 10-9 otc counter 10-16 overrun error flag bit (or) 8-14 p pab 1-13 pag 1-10 parity error bit (pe) 8-14 pb0epb7 signals 2-18 pb10 signal 2-19 pb11 signal 2-20 pb12 signal 2-20 pb13 signal 2-21 pb14 signal 2-22 pb15 signal 2-23 pb8 signal 2-18 pb9 signal 2-19 pc register 1-10 pc0 signal 2-24 pc0-pc20 bits 9-9 pc1 signal 2-25 pc2 signal 2-25 pc3 signal 2-26 pc4 signal 2-26 pc5 signal 2-27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . p motorola dsp56309um/d i-9 pcap signal 2-8 pcrc register 7-43 pcrd register 7-43 pcre register 8-27 pctl register bits 0e11?multiplication factor bits (mf0emf11) 4-18 bit 16?xtal disable bit (xtld) 4-18 bits 20e23?predivider factor bits (pd0epd3) 4-18 pcu 1-10 pd bits 4-18 pd0 signal 2-28 pd1 signal 2-28 pd2 signal 2-29 pd3 signal 2-30 pd4 signal 2-30 pd5 signal 2-31 pdb 1-13 pdc 1-10 pdrc register 7-45 pdrd register 7-45 pdre register 8-28 pe bit 8-14 pe0 signal 2-32 pe1 signal 2-32 pe2 signal 2-33 peripheral i/o expansion bus 1-13 pic 1-10 pinit/nmi 2-9 pll initial 2-8 pl0-pl20 bits 9-7 pl21-pl22 bits 9-7 pll 1-11 , 2-3 pll capacitor signal 2-8 pll initialize signal 2-9 pll signals 2-7 pm0epm7 bits 7-11 port a 2-3 , 2-9 port b 2-3 , 2-4 , 2-19 , 5-3 port b 10 signal (pb10) 2-19 port b 11 signal (pb11) 2-20 port b 12 signal (pb12) 2-20 port b 13 signal (pb13) 2-21 port b 14 signal (pb14) 2-22 port b 15 signal (pb15) 2-23 port b 8 signal (pb8) 2-18 port b 9 signal (pb9) 2-19 port b signal (pb0epb7) 2-18 port c 2-3 , 2-4 , 2-24 , 2-25 , 2-28 , 5-3 port c 0 signal (pc0) 2-24 port c 1 signal (pc1) 2-25 port c 2 signal (pc2) 2-25 port c 3 signal (pc3) 2-26 port c 4 signal (pc4) 2-26 port c 5 signal (pc5) 2-27 port c control register (pcrc) 7-43 port c data register (pdrc) 7-45 port c direction register (prrc) 7-44 port d 2-3 , 2-4 , 2-28 , 5-4 port d 0 signal (pd0) 2-28 port d 1 signal (pd1) 2-28 port d 2 signal (pd2) 2-29 port d 3 signal (pd3) 2-30 port d 4 signal (pd4) 2-30 port d 5 signal (pd5) 2-31 port d control register (pcrd) 7-43 port d data register (pdrd) 7-45 port d direction register (prrd) 7-44 port e 2-3 , 2-32 , 5-4 port e 0 signal (pe0) 2-32 port e 1 signal (pe1) 2-32 port e 2 signal (pe2) 2-33 port e control register (pcre) 8-27 port e data register (pdre) 8-28 port e direction register (prre) 8-27 power 2-3 , 2-5 ground 2-6 low 1-7 management 1-7 standby modes 1-7 power input address bus 2-5 bus control 2-5 data bus 2-5 essi 2-6 host interface 2-5 pll 2-5 quiet 2-5 sci 2-6 timer 2-6 predivider factor bits (pd) 4-18 prescale modulus select bits (pm0epm7) 7-11 prescaler counter 9-7 prescaler counter value bits (pc0-pc20) 9-9 prescaler load value bits (pl0-pl20) 9-7 prescaler range bit (psr) 7-11 prescaler source bits (pl21-pl22) 9-7 program address bus (pab) 1-13 program address generator (pag) 1-10 program control unit (pcu) 1-10 program counter register (pc) 1-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . r i-10 dsp56309um/d motorola program data bus (pdb) 1-13 program decode controller (pdc) 1-10 program interrupt controller (pic) 1-10 program memory expansion bus 1-13 program ram 3-6 programming sheets ? see appendix b prrc register 7-44 prrd register 7-44 prre register 8-27 psr bit 7-11 r r/w bit 10-6 r8 bit 8-15 ras0 eras3 signals 2-10 rcm bit 8-17 rd signal 2-10 rdf bit 7-30 rdrf bit 8-14 re bit 7-26 , 8-10 read enable signal (rd ) 2-10 read/write command bit (r/w ) 10-6 receive byte registers (rxh, rxm, rxl) 6-28 receive clock mode source bit (rcm) 8-17 receive data register (rx) 7-33 receive data register full bit (rdf) 7-30 receive data register full bit (rdrf) 8-14 receive data register full bit (rxdf) 6-26 receive data signal (rxd) 8-4 receive exception interrupt enable bit (reie) 7-27 receive frame sync flag bit (rfs) 7-28 receive host request signal (hrrq /hrrq) 2-23 receive interrupt enable bit (rie) 7-26 , 8-11 receive last slot interrupt enable bit (rlie) 7-27 receive request enable bit (rreq) 6-23 receive shift register 7-33 receive slot mask registers (rsma, rsmb) 7-35 received bit 8 address bit (r8) 8-15 receiver enable bit (re) 8-10 receiver overrun error flag bit (roe) 7-29 receiver wakeup enable bit (sbk) 8-9 register select bits (rs0ers4) 10-5 reie bit 7-27 , 8-13 reserved bits in cra register 7-11 , 7-13 , 7-14 in hbar register bits 5e15 6-12 in hcr register bits 5e15 6-10 in hpc register bit 7 6-14 in hsr register bits 5e15 6-11 in icr register bit 6 6-24 in isr register bit 5 6-27 bit 6 6-27 in obcr register bits 12e15 10-15 in oscr register bit 5, bits 8e23 10-9 in tcsr register bits 3, 10, 14, 16e19, 22, 23 9-15 in tpcr 9-9 in tplr 9-8 reset 2-14 reset signal 2-14 reverse-carry adder 1-9 rfs bit 7-28 rie bit 7-26 , 8-11 rlie bit 7-27 roe bit 7-29 rom bootstrap 3-7 row address strobe signals ras0eras3 2-10 rreq bit 6-23 rs0ers4 bits 10-5 rsma, rsmb registers 7-35 rw00erw01 bits 10-12 rw10erw11 bits 10-13 rwu bit 8-9 rx register 7-33 rxd 2-32 rxd signal 8-4 rxdf bit 6-26 rxh, rxm, rxl registers 6-28 s sample/preload instruction 11-9 sbk bit 8-9 sc register 1-11 sc0 signal 7-6 , 7-8 sc00 signal 2-24 sc01 signal 2-25 sc02 signal 2-25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . s motorola dsp56309um/d i-11 sc1 signal 7-7 sc10 2-28 sc11 2-28 sc12 2-29 sccr register 8-15 bits 0e11?clock divider bits (cd0ecd11) 8-16 bit 12?clock out divider bit (cod) 8-16 bit 13?sci clock prescaler bit (scp) 8-17 bit 14?receive clock mode source bit (rcm) 8-17 bit 15?transmit clock source bit (tcm) 8-18 scd0 bit 7-16 scd1 bit 7-16 scd2 bit 7-16 sci 1-16 , 2-4 , 2-32 exceptions 8-26 idle line 8-26 receive data 8-26 receive data with exception status 8-26 timer 8-26 transmit data 8-26 gpio functionality 8-27 initialization 8-24 example 8-25 operating mode asynchronous 8-21 synchronous 8-21 operating modes asynchronous 8-21 programming model 8-4 reset 8-22 state after reset 8-23 transmission priority preamble, break, and data 8-26 sci (gpio) 5-4 sci clock control register (sccr) 8-15 sci clock polarity bit (sckp) 8-12 sci clock prescaler bit (scp) 8-17 sci exceptions receive data 8-26 sci pins rxd, txd, sclk 8-3 sci receive register (srx) 8-19 sci receive with exception interrupt bit (reie) 8-13 sci serial clock signal (sclk) 8-4 sci shift direction bit (ssftd) 8-9 sci status register (ssr) 8-13 sci transmit register (stx) stx register 8-20 sck signal 7-5 sck0 2-26 sck1 signal 2-30 sckd bit 7-16 sckp bit 8-12 sclk signal 2-33 , 8-4 scp bit 8-17 scr register bits 0-2?word select bits (wds0-wds2) 8-8 bit 3?sci shift direction bit (ssftd) 8-9 bit 4?send break bit (sbk) 8-9 bit 5?wakeup mode select bit (wake) 8-9 bit 6?receiver wakeup enable bit (rwu) 8-9 bit 7?wired-or mode select bit (woms) 8-10 bit 8?receiver enable bit (re) 8-10 bit 9?transmitter enable bit (te) 8-10 bit 10?idle line interrupt enable bit (ilie) 8-11 bit 11?receive interrupt enable bit (rie) 8-11 bit 12?transmit interrupt enable bit (tie) 8-12 bit 13?timer interrupt enable bit (tmie) 8-12 bit 14?timer interrupt rate bit (stir) 8-12 bit 15?sci clock polarity bit (sckp) 8-12 bit 16?sci receive with exception interrupt enable bit (reie) 8-13 select sc1 as transmitter 0 drive enable bit (ssc1) 7-14 send break bit (sbk) 8-9 serial clock signal (sck) 7-5 serial clock signal (sck0) 2-26 serial clock signal (sck1) 2-30 serial clock signal (sclk) 2-33 serial communication interface (sci) 2-32 serial communications interface (sci) 1-16 , 2-3 , 8-3 serial control 0 direction bit (scd0) 7-16 serial control 0 signal (sc0) 7-6 , 7-8 serial control 0 signal (sc00) 2-24 serial control 0 signal (sc10) 2-28 serial control 1 direction bit (scd1) 7-16 serial control 1 signal (sc01) 2-25 serial control 1 signal (sc1) 7-7 serial control 1 signal (sc11) 2-28 serial control 2 direction bit (scd2) 7-16 serial control 2 signal (sc02) 2-25 serial control 2 signal (sc12) 2-29 serial input flag 0 bit (if0) 7-28 serial input flag 1 bit (if1) 7-28 serial output flag bits (of0eof1) 7-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . t i-12 dsp56309um/d motorola serial protocol in once module 10-22 serial receive data signal (rxd) 2-32 serial receive data signal (srd) 7-4 serial receive data signal (srd0) 2-26 serial receive data signal (srd1) 2-30 serial transmit data signal (std) 7-4 serial transmit data signal (std0) 2-27 serial transmit data signal (std1) 2-31 serial transmit data signal (txd) 2-32 shfd bit 7-17 shift direction bit (shfd) 7-17 signal groupings 2-3 signals 2-3 functional grouping 2-4 single data strobe 2-4 sixteen-bit compatibility 3-3 size register (sz) 1-10 software debug occurrence bit (swo) 10-8 sp 1-11 sr register 1-10 sram interfacing 1-13 srd signal 7-4 srd0 2-26 srd1 2-30 srx read as srxl, srxm, srxh 8-19 srx register 8-19 ss 1-11 ssc1 bit 7-14 ssftd bit 8-9 ssisr register 7-27 bit 0?serial input flag 0 bit (if0) 7-28 bit 1?serial input flag 1 bit (if1) 7-28 bit 2?transmit frame sync flag bit (tfs) 7-28 bit 3?receive frame sync flag bit (rfs) 7-28 bit 4?transmitter underrun error flag bit (tue) 7-29 bit 5?receiver overrun error flag bit (roe) 7-29 bit 6?transmit data register empty bit (tde) 7-29 bit 7?receive data register full bit (rdf) 7-30 ssr register 8-13 bit 1?transmitter empty bit (trne) 8-13 bit 2?receive data register full bit (rdrf) 8-14 bit 2?transmit data register empty bit (tdre) 8-13 bit 3?idle line flag bit (idle) 8-14 bit 4?overrun error flag bit (or) 8-14 bit 5?parity error bit (pe) 8-14 bit 6?framing error flag bit (fe) 8-15 bit 7?received bit 8 address bit (r8) 8-15 stack counter register (sc) 1-11 stack pointer (sp) 1-11 standby mode stop 1-7 wait 1-7 status register (sr) 1-10 std signal 7-4 std0 2-27 std1 2-31 stir bit 8-12 stop standby mode 1-7 stx register read as stxl, stxm. stxh, and stxa 8-20 swo bit 10-8 syn bit 7-18 system stack (ss) 1-11 sz register 1-10 t ta signal 2-11 tap 1-11 tap controller 11-6 tc0etc3 bits 9-10 tcie 9-10 tck pin 11-5 tck signal 2-35 tcm bit 8-18 tcr register 9-16 tcsr register 9-9 bit 0?timer enable bit (te) 9-9 bits 4e7?timer control bits (tc0etc3) 9-10 bit 8?inverter bit (inv) 9-11 bit 13?data output bit (do) 9-14 reserved bits?bits 3, 10, 14, 16e19, 22, 23 9-15 tde bit 7-29 tdi pin 11-5 tdi signal 2-35 tdo signal 2-36 tdre bit 8-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . t motorola dsp56309um/d i-13 te bit 8-10 , 9-9 te0 bit 7-24 te1 bit 7-23 te2 bit 7-22 teie bit 7-27 test access port (tap) 1-11 , 11-3 test clock input pin (tck) 11-5 test data input pin (tdi) 11-5 test mode select input pin (tms) 11-5 test reset input pin (trst ) 11-5 tfs bit 7-28 tie bit 7-26 , 8-12 time slot register (tsr) 7-34 timer special cases 9-27 timer (gpio) 5-4 timer 0 signal (tio0) 2-34 timer 1 signal (tio1) 2-34 timer 2 signal (tio2) 2-35 timer control bits (tc0etc3) 9-10 timer control/status register (tcsr) 9-9 timer count register (tcr) 9-16 timer enable bit (te) 9-9 timer interrupt enable bit (tmie) 8-12 timer interrupt rate bit (stir) 8-12 timer mode mode 0?gpio 9-17 mode 1?timer pulse 9-18 mode 2?timer toggle 9-19 mode 3?timer event counter 9-20 mode 4?measurement input width 9-21 mode 5?measurement input period 9-22 mode 6?measurement capture 9-23 mode 7?pulse width modulation 9-24 mode 8?reserved 9-25 mode 9?watchdog pulse 9-25 mode 10?measurement toggle 9-26 modes 11e15?reserved 9-27 timer module 1-17 , 2-34 architecture 9-3 programming model 9-5 timer block diagram 9-4 timer prescaler count register (tpcr) 9-8 timer prescaler load register (tplr) 9-7 timers 2-3 , 2-4 tlie bit 7-26 tme bit 10-8 tmie bit 8-12 tms pin 11-5 tms signal 2-36 to bit 10-9 toie 9-9 tpcr register 9-8 bits 0-20?prescaler counter value bits (pc0-pc20) 9-9 bit 21-23?reserved bits 9-9 reserved bits?bits 21-23 9-9 tplr register 9-7 bits 0-20?prescaler load value bits (pl0-pl20) 9-7 bits 21-22?prescaler source bits (pl0-pl20) 9-7 bit 23?reserved bit 9-8 reserved bit?bit 23 9-8 trace buffer 10-21 trace mode enabling 10-18 in once module 10-15 trace mode enable bit (tme) 10-8 trace occurrence bit (to) 10-9 transfer acknowledge signal 2-11 transmit 0 enable bit (te0) 7-24 transmit 1 enable bit (te1) 7-23 transmit 2 enable bit (te2) 7-22 transmit byte registers (txh, txm, txl) 6-29 transmit clock source bit (tcm) 8-18 transmit data register empty bit (tde) 7-29 transmit data register empty bit (tdre) 8-13 transmit data register empty bit (txde) 6-27 transmit data signal (txd) 8-4 transmit exception interrupt enable bit (teie) 7-27 transmit frame sync flag bit (tfs) 7-28 transmit host request signal (htrq /htrq) 2-22 transmit interrupt enable bit (tie) 7-26 , 8-12 transmit last slot interrupt enable bit (tlie) 7-26 transmit request enable bit (treq) 6-23 transmit shift registers 7-33 transmit slot mask registers (tsma, tsmb) 7-34 transmitter empty bit (trne) 8-13 transmitter enable bit (te) 8-10 transmitter ready bit (trdy) 6-27 transmitter underrun error flag bit (tue) 7-29 trdy bit 6-27 treq bit 6-23 triple timer module 1-17 trne bit 8-13 trst pin 11-5 tsma, tsmb registers 7-34 tsr register 7-34 tue bit 7-29 tx2, tx1, tx0 registers 7-34 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . v i-14 dsp56309um/d motorola txd signal 2-32 , 8-4 txde bit 6-27 txh, txm, txl registers 6-29 v vba register 1-10 vector base address register (vba) 1-10 w wait standby mode 1-7 wake bit 8-9 wakeup mode select bit (wake) 8-9 wds0-wds2 bits 8-8 weak keeper 2-24 , 2-25 , 2-26 , 2-27 , 2-28 , 2-29 , 2-30 , 2-31 , 2-32 , 2-33 , 2-34 , 2-35 wired-or select bit (woms) 8-10 wl0ewl1 bits 7-14 woms bit 8-10 word length control bits (wl0ewl1) 7-14 word select bits (wds0-wds2) 8-8 wr signal 2-10 write enable signal 2-10 x x data ram 3-6 x memory address bus (xab) 1-13 x memory data bus (xdb) 1-13 x memory expansion bus 1-13 xab 1-13 xdb 1-13 xtal 2-8 xtal disable bit (xtld) 4-18 xtld bit 4-18 y y data ram 3-7 y memory address bus (yab) 1-13 y memory data bus (ydb) 1-13 y memory expansion bus 1-13 yab 1-13 ydb 1-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1 2 3 4 6 7 5 11 8 9 10 dsp56309 overview signal/connection descriptions memory configuration core configuration general purpose i/o host interface (hi08) enhanced synchronous serial interface serial communication interface (sci) timer module on-chip emulation module jtag port c bsdl listing i index d programming reference a bootstrap program b equates f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1 2 3 4 6 7 5 11 8 9 10 dsp56309 overview signal/connection descriptions memory configuration core configuration general purpose i/o host interface (hi08) enhanced synchronous serial interface serial communication interface (sci) timer module on-chip emulation module jtag port c bsdl listing i index d programming reference a bootstrap program b equates f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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